本論文提出一個應用於人工智慧邊緣裝置的全類比式記憶體內運算處理器。以往的記憶體內運算架構都須藉由數位類比轉換器、類比數位轉換器以及大量的儲存器來實現神經網路層間訊號傳遞，然而量化雜訊將有可能限制神經網路的準確率，故本論文提出使用放大器模擬神經元訊號傳輸，藉此增加神經網路精度及降低儲存器的數量，實現感測器旁的全類比式神經網路運算的方式。為此，本論文提出四種技巧來實現此電路: (1)基於靜態隨機存取記憶體單元的九顆電晶體運算單元、以電荷重分布的技術達成相對於電流方式更為線性的乘加運算；(2)依權重比例切分電容，並以電荷平均的技術配合電容開關切換，創造出有號數八位元權重運算，相較於傳統數位移位加法器加總的方式，所提出的方法不僅快又省電，且不受量化雜訊限制；(3)結合激活函數與零點交越式放大器避免不必要的傳輸放大，並解決傳輸電路靜態功耗的問題；(4)過充消除技巧來解決零點交越式放大器放大過程所產生的過充現象。
本晶片使用台積電180nm CMOS 1P6M製程製造，核心面積為20.98 mm2 實現類比輸入 / INT8權重 / 類比輸出之運算，784x100x10的全連接層神經網路。在1.3V及100MHz時脈操作下，運算吞吐量為441-GOPS，乘加運算為效1880-TOPS/W，全網路運算能效為117-TOPS/W，MNIST資料集辨識準確率約為91.48%。

This thesis presents a fully analog processing Computing-in-Memory (CIM) chip designed for artificial intelligence (AI) edge devices. In the past, conventional CIM architectures typically used digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and extensive registers to achieve signal transmission between layers of neural networks. However, quantization noise plays a non-ignorable role in the accuracy of neural networks. Therefore, this thesis proposes the use of amplifiers to imitate signal transmission between neurons, aiming to enhance the accuracy of neural networks and reduce the number of registers, thereby realizing a fully analog neural network computation approach at the sensor. To achieve this, the thesis proposes four techniques for this approach: (1) A static random-access memory (SRAM)-based 9T1C computing cell performs the Multiply-Accumulate (MAC) computation through charge redistribution, achieving better linearity compared to current-domain computation. (2) Capacitors are split based on binary-weight ratios and combined with switching capacitor (SC) method to create signed 8-bit weighted MAC through charge sharing. Comparing with conventional digital shifter-adder-based method, this method is not only faster and more power-efficient but also offers high accuracy if the noise floor is sufficiently low. (3) Integrate the ReLU function into the zero-crossing amplifier to avoid unnecessary signal amplification, resulting in a significant reduction in energy consumption. (4) The overshoot cancellation technique for resolving the overshoot errors in the zero-crossing-based amplification.
The proof-of-concept prototype was fabricated in TSMC's 180 nm CMOS standard 1P6M technology. The core area is 20.98 mm2 and supports an analog-input / INT8-weight / analog-output MAC operation and 784x100x10 fully connected layers. Measurements indicate that at a 1.3V power supply, with a clock frequency of 100 MHz the system, it achieves a throughput of 441-GOPS, an energy efficiency of 1880-TOPS/W for MAC operations, and a whole-neural-network energy efficiency of 117-TOPS/W. The inference accuracy for the MNIST database is about 91.48%.

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