本論文提出了語音辨識與語音壓縮系統之相關硬體架構及晶片設計。在語音辨認方面包括了MFCC參數擷取硬體架構及鑑別式拜氏類神經網路(Discriminative Bayesian neural net-work)晶片。而在語音壓縮方面，提出了1.6Kbps低位元率語音編碼器硬體架構，最後我們亦設計了一個同時具語音辨識及壓縮功能之可攜式之語音行事曆。

　　In this dissertation, we propose several VLSI architectures and implementation for the speech recognition and compression systems. In the first part, the first chip for speech features extraction based on MFCC algorithm is proposed. The chip is implemented as an IP (Intellectual Property), which is suitable to be adopted in a speech recognition system on a chip. The computational complexity and memory requirement of MFCC algorithm is analyzed in detail and improved greatly. The hybrid table-look up scheme is presented to deal with the elementary function value in the MFCC algorithm. Fixed-point arithmetic is adopted to reduce the cost under the accuracy studies of finite word length effect. Finally, the area-efficient design is implemented successfully into the single Xilinx XC4062XL FPGA.

　　In addition, we present an efficient VLSI architecture for the stand-alone application of a speech recognition system based on discriminative Bayesian neural network (DBNN). Regarding the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed first. In association with the BDU, we propose a template-serial architecture for the path distance accumulation to perform the recognition procedure. A corresponding architecture is also developed to accelerate the discriminative training procedure. It contains the intelligent look-up table for the sigmoid function. In comparison to the traditional one-table method, the memory size reduces drastically with only slight loss of accuracy. Combining the proposed hardware accelerators with the cost efficient programmable core, we took the most out of both programmable and application-specific architectures, including performance, design complexity, and flexibility.

　　In the speech coding part, we present a single-chip design for a low bit rate speech vocoder. This coder has fine quality synthesized speech, even though the bit rate is only 1.6 Kbps. For efficiency, we designed separate dedicated architectures for the encoding and the decoding modules. For lowering the cost, these architectures are integrated by resource sharing, requiring only one multiplier and adder. The proposed design was experimentally verified via semi custom chips using 0.35 ?m CMOS single-poly-four-metal technology on a die size approximately 2.26 2.25 mm2.

　　Finally, this dissertation presents the design of a speech recognition and compression chip for portable memopad devices, especially suitable for use by the visually impaired. The proposed chip design is based on several cores of which they can be regarded as intellectual property (IP) cores to be used for a variety of speech-related application systems. A cepstrum extraction core and a dynamic warping core are designed for mapping the speech recognition algorithms. In the cepstrum extraction core, a novel architecture computes the autocorrelation between the overlapping frames using two pairs of shift registers and an intelligent accumulation procedure. The architecture of the dynamic time warping core uses only a single processing element, and is based on our extensive study of the relationship among the nodes in the dynamic time warping lattice. Bit rate is the key factor affecting the memory size for speech compression; therefore, a very low bit-rate speech coder is used. The speech coder exploits a line-spectrum-based interpolation method, which yields fine quality synthesized speech despite the low 1.6Kbps bit rate. The 1.6K vocoder core is cost-effective, and it integrates both encoder and decoder algorithms. The proposed design has been tested via hardware simulations on Xilinx Virtex series FPGAs.

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