藍相液晶因具有次毫秒之反應時間、廣視角與不需配向膜以節省成本等優點，被視為是下一世代的液晶顯示技術之一。然而藍相液晶需高達30伏特以上之操作電壓才足以展現其最大之光穿透度，但現行顯示器資料驅動電路的最大輸出電壓卻僅約15伏特。更改畫素電極形狀與提升藍相液晶之克爾常數為降低其操作電壓於15伏特甚至10伏特以下的有效方法，但後者會使得藍相液晶之等效電容大幅增加，增加其被充電的困難度。傳統1T2C畫素電路並無法克服上述兩者任一之情況。而現今無論是液晶面板或是有機發光二極體面板皆會以薄膜電晶體實現的閘極驅動電路操作二維的畫素矩陣，但薄膜電晶體於長時間使用下的臨界電壓飄移與其寄生電容對閘極驅動電路輸出節點造成之時脈饋入效應都會導致輸出波型不穩定與電路的操作失效。
為了解決上述問題，本論文提出三個新式藍相液晶畫素電路與三個新式閘極驅動電路。第一個電路為針對高操作電壓藍相液晶、採用非晶氧化銦鎵鋅薄膜電晶體之3T2C畫素架構，其以一個提供三個電壓準位之訊號線搭配現行資料驅動電路，利用電荷分享的方式使得施加於藍相液晶的最高電壓可提升至20伏特以增加藍相液晶穿透度。模擬結果證明此電路設計適用於更新頻率120赫茲、解析度為Full High Definition (FHD, 1920 × 1080)之操作規格。相較於傳統1T2C畫素電路，此新式電路雖然能產生較高的電壓值，但是此結果尚不足以使藍相液晶展示其最高之光穿透度。為進一步改善前述的情況，則提出第二個為同樣採用非晶氧化銦鎵鋅薄膜電晶體之2T3C畫素架構，其利用兩條電容耦合用訊號線且同樣配合現行資料驅動電路之電壓輸出規格，即使得藍相液晶所能夠接受到的最高電壓大幅提升至30伏特，足以致使藍相液晶展現其最高穿透度而改善面板亮度不足之問題。此設計也被實際導入面板而製造出一10.1吋之展示機並且成功點亮。第三個電路則是聚焦於低操作電壓藍相液晶所面臨高等效電容之問題而提出一採用非晶氧化銦鎵鋅薄膜電晶體之2T3C畫素架構與實際之資料驅動電路搭配，藉由電容耦合的方式抬升開關電晶體之閘極電壓以大幅提升畫素充放電能力。與傳統1T2C畫素結構相比，此電路即使於更新頻率120赫茲、解析度為FHD之操作規格下，仍然能夠將藍相液晶充電至預期的資料電壓值。第四個電路為一採用非晶矽薄膜電晶體之10T1C閘極驅動電路，目的為應用在大尺寸之面板，此利用兩組低頻且互為反向之交流訊號交互穩定電路之輸出節點並同時施加交流反向偏壓於非晶矽薄膜電晶體以抑制臨界電壓的飄移，且整體的功率消耗也因為低頻的操作得到改善。在歷經840小時於攝氏100度的量測環境下，電路輸出波型的上升與下降時間皆維持高度的一致性且單級之功率消耗僅為98.7微瓦。第五個電路是一採用非晶矽薄膜電晶體之12T1C閘極驅動電路，希冀能應用在大尺寸之面板，其藉由時脈訊號的調整切換可應用於較低速操作之二維畫面顯示或者是較高速操作之三維畫面顯示。量測結果證明此架構能夠於攝氏100度運作240個小時，且應用於二維及三維畫面顯示之波型皆無失真且維持高度的穩定性。第六個電路則是應用高電子遷移率、高電性穩定之低溫多晶矽薄膜電晶體設計一極精簡之3T2C閘極驅動電路，主要應用目標為小尺寸的行動裝置面板，該結構以反向電容耦合的方式抵銷由寄生電容造成之時脈饋入效應並將上拉電晶體同時作為穩壓電晶體之用途，此設計可以大幅減少所需的電晶體數量使面板的邊框達到極致窄化的特色。模擬結果顯示所提出的概念能有效地以簡易的電路設計抑制輸出波型的雜訊，且電路佈局面積僅為119微米乘上68微米。

The blue-phase liquid crystal (BPLC) is characterized by its sub-millisecond response time, wide viewing angle, and no need for alignment layers, and therefore considered as one of the next-generation display technologies. However, to obtain the peak transmittance of BPLC, a high operating voltage (above 30 V) is necessary. Unfortunately, data driver integrated circuits (ICs) practically used in the display industry only provide a maximum output voltage of around 15 V. Changing shapes of pixel electrodes and enlarging the Kerr constant of BPLC are effective to decrease the operating voltage below 15 V or even 10 V, but the latter approach also results in increase in the effective capacitance of BPLC. The conventional one-transistor two-capacitor (1T2C) pixel circuit is no longer able to overcome either situation. On other hand, both LC and organic light-emitting diode (OLED) pixel arrays are nowadays driven by thin-film-transistor-based (TFT-based) gate driver circuits on glass substrates. Nevertheless, threshold voltage shifts in TFTs and/or parasitic capacitors, inducing the clock feed-through effect, bring about unstable output waveforms and circuit malfunctions.
This dissertation presents three novel BPLC pixel circuits and three novel gate driver circuits, whose effectiveness is verified by simulations and measurements. In terms of BPLC with a high operating voltage, the first one develops an amorphous-indium-gallium-zinc-oxide-TFT-based (a-IGZO-TFT-based) 3T2C pixel circuit which employs a three-voltage-level signal and the specification of practical data driver ICs to perform charge-sharing method, raising the maximum voltage across BPLC to 20 V to achieve a higher transmittance compared with that obtained by 1T2C pixel circuit. Simulation results indicate this circuit is suitably operated at a 120-Hz frame rate and the resolution of Full High Definition (FHD, 1920 × 1080). However, 20 V is still not high enough to secure the peak transmittance of BPLC. The second pixel circuit is an a-IGZO-TFT-based 2T3C structure which greatly increases the maximum voltage across BPLC to 30 V by adopting two two-voltage-level signals with the capacitor coupling method. The circuit also leads to a successful 10.1-inch prototype BPLCDs. Considering the low-operating-voltage and high-effective-capacitance BPLC cooperating with the practical data driver ICs, the third circuit is also based on a-IGZO TFTs and a 2T3C pixel structure in which the gate voltage of the switch TFT is up boosted, greatly enhancing charge and discharge capabilities of a pixel. In contrast to 1T2C pixel circuit, simulation results demonstrate that this circuit is more capable of charging BPLC to expected data voltages at a 120-Hz frame rate and the FHD resolution. The fourth is an a-Si-TFT-based low-power 10T1C gate driver circuit which utilizes two low-frequency signals to apply a reverse bias to TFTs to suppress threshold voltage shifts and alternately stabilize output waveforms. Measurement results show that this circuit can be stably operated at 100 ºC for over 840 hours, and its power consumption per stage is only 98.7 µW. The next one is an a-Si-TFT-based 12T1C gate driver circuit which is able to work at either a low speed for 2D images or a high speed for 3D images. Measurement results reveal that the circuit alternately being switched between the 2D mode and the 3D mode can sustain 100-ºC operation for over 240 hours. The last is a low-temperature-polycrystalline-silicon-TFT-based (LTPS-TFT-based) 3T2C gate driver circuit aiming at ultra-narrow-bezel display panels. This structure uses an inverse-coupling method to restrain the noise caused by the clock feed-through effect and exploits the pull-up TFT to periodically stabilize the output waveform. The layout area is only 119 µm × 68 µm.

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