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研究生：	蔡忠仰 Tsai, Chung-Yang
論文名稱：	以基體驅動具可規劃能力之低壓贏者通吃電路設計與實現 Design and Implementation of Bulk-Driven Low-Voltage CMOS Winner-Take-All Circuit with Programmable Capability
指導教授：	劉濱達 Liu, Bin-Da
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2003
畢業學年度：	91
語文別：	中文
論文頁數：	85
中文關鍵詞：	贏者通吃、基體驅動、低壓
外文關鍵詞：	winner take all, bulk driven, low voltage
相關次數：	點閱：47 下載：2
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類比式贏者通吃(Winner-Take-All，簡稱WTA)電路主要之功能為在諸多的類比輸入訊號中，判別何者具有最大的輸入值。此功能主要應用於向量量化、圖形辨識、類神經網路、模糊控制器與非線性訊號處理等。因積體電路(IC)的製程的不斷改善與元件尺寸最小化(scale down)的需求，為提高電路運作的可靠度，低電壓電路設計為近來重要的研究方向之一。
本研究設計一新式類比CMOS電路，具有可規劃k-WTA或 k-LTA能力之贏者通吃電路。此電路藉由採用基體驅動(bulk-driven)之技巧，使電路所需要之工作電壓下降至1 V，並利用雙向比較(up-and-down searching)之方式，提升電路運算速度。在不需修改電路架構之前提下，此贏者通吃電路藉由一組數位控制訊號，來規劃此贏者通吃電路執行k-WTA或k-LTA之功能。
本論文使用TSMC 1P5M 0.25 μm的製程來實現所設計之晶片，晶片面積為630 μm x 580 μm。模擬結果顯示此WTA電路在5 mV之精確度下所需之反應時間為50 μs，且具全幅輸入範圍，動態功率消耗約2 mW。
本論文並且設計一低電壓圖樣辨識之相似值測量電路來作為此贏者通吃電路之應用，該圖樣辨識電路以實現Hamming Metric為核心。硬體實現使用相同的製程，晶片面積為800 μm x 780 μm。此晶片內預存8個圖樣，每個圖樣皆為6 4圖素(pixel)，並允許一組輸入圖樣。

Winner-take-all (WTA) circuit identifies the largest input variable and inhibits the remaining variables, which is the major function in vector quantization, pattern classification, artificial neural network, and non-linear signal processing unit. Since CMOS fabrication is continuously improving via thinner gate oxides, reduced device size, and so forth, the voltage supply of VLSI circuit in sub-micron technologies must be reduced.
In this paper, a new analog CMOS WTA circuit with programmable k-WTA and k-LTA capabilities is proposed. Based on the bulk-driven technique, the supply voltage of the circuit is reduced to 1 V. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-WTA function or k-LTA function is programmable, without modifying circuit structure.
The WTA circuit has been fabricated by TSMC 0.25 μm 1P5M process with 28 S/B package. About 1980 transistors are used with silicon area of 630 μm x 580 μm. The results of simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.
Finally, a similarity measurement circuit for pattern identification has been designed as the application of WTA. Based on Hamming Metric, similarity measurements of various patterns are achieved. The circuit has been also fabricated by TSMC 0.25 μm 1P5M process with 28 S/B package. About 3080 transistors are used with silicon area of 800 μm x 780 μm.

緒論........................................1
1 相關研究發展現況...........................1
2 研究動機...................................1
3 各章節摘要.................................2
低壓比較器之架構設計........................3
1 低壓電路設計方式...........................3
1.1 低壓電路設計概述.........................3
1.2 次臨界區域...............................4
1.3 電位平移.................................6
1.4 自我疊接.................................6
1.5 浮動閘極.................................8
1.6 基體驅動................................10
1.7 低壓電路設計方式之比較..................11
2 基體驅動比較器設計........................12
2.1 基體驅動電晶體之特性....................12
2.2 基體驅動比較器之電路架構................16
可規劃低壓WTA架構設計與實現................18
1 架構簡介..................................18
1.1 定義....................................18
1.2 架構....................................18
2 電路實現..................................22
2.1 低電壓比較器............................22
2.2 D型正反器與多工器.......................23
2.3 計算單元................................24
2.4 輸出抑制與輸出選擇單元..................25
2.5 選擇編碼器..............................25
2.6 時脈產生電路............................28
模擬結果與量測考量.........................30
1 模擬結果..................................30
2 實體佈局..................................34
3 接腳定義..................................38
4 量測考量..................................39
5 規格列表..................................40
6 效能比較..................................41
圖樣辨識之相似值測量電路...................43
1 應用簡介..................................43
2 架構設計..................................45
2.1 定義....................................45
2.2 架構簡介................................46
3 電路實現..................................47
3.1 相似性量測..............................47
3.2 平均值電路..............................47
3.3 倍壓產生電路/可重置倍壓產生電路.........51
3.4 輸入測試圖樣電路........................52
4 模擬結果與量測考量........................53
4.1 模擬結果................................53
4.2 實體佈局................................57
4.3 接腳定義................................60
4.4 量測考量................................60
4.5 規格列表................................62
4.6 討論與改善..............................63
5 整合應用電路..............................64
5.1 模擬結果................................65
5.2 討論....................................67
非理想因素之討論...........................68
1 非理想因素對可規劃低壓WTA電路之影響.......68
1.1 低壓比較器之輸入非理想..................68
1.2 低壓比較器offset........................70
1.3 WTA電路之PSRR模擬.......................73
1.4 當WTA電路之輸入訊號存在兩個相等電位.....75
1.5 當WTA電路之斜坡電壓斜率不一.............75
2 非理想因素對圖樣辨識相似值量測電路之影響..78
2.1 相似性量測與平均值電路之不匹配性........78
2.2 整合應用電路之負載效應..................80
結論與未來展望.............................81
1 結論......................................81
2 未來展望..................................82
參考文獻......................................83
                                    

[1] R. Lippmann, “An introduction to computing with neural nets,” IEEE ASSP Mag., vol. 4, pp. 4-22, Apr. 1987.
[2] J. Lazaro, R. Ryckebusch, M. A. Mahowald, and C. A. Mead, “Winner-take-all networks of O(N) complexity,” Advances in Neural Inform. Processing Syst., vol. 1, pp. 703-711, 1989.
[3] B. Sekerkiran and U. Cilingiroglu, “A CMOS K-winners-take-all circuit with O(N) complexity,” IEEE Trans. Circuits Syst. II, vol.46, no. 1, pp. 1-4, Jan. 1999.
[4] Y. C. Hung and B. D. Liu, “A scalable high-precision CMOS max/min circuit using single comparator,” in Proc. IEEE 1st AP-ASIC’99, Seoul, Korea, Aug. 1999, pp. 206-209.
[5] Y. C. Hung and B. D. Liu, “A 1.2-V rail-to-rail analog CMOS rank-order filter with k-WTA capability,” Analog Integr. Circuits Signal Process., vol. 32, pp. 219-230, Sep. 2002.
[6] K. Langen and J. H. Huijsing, “Compact low-voltage power efficient operational amplifier cells for VLSI”, IEEE J. Solid-State Circuits, vol. 33, no. 10, pp.1483-1496, Oct. 1998.
[7] S. S. Rajput and S. S. Jamuar, “Low voltage analog circuit design techniques”, IEEE Circuits Syst. Mag., vol. 2, pp.24-42, 2002.
[8] B. J. Hosticka, W. Brockherde, D. Hammerschmidt, and R. Kokozinski,“Low-voltage CMOS analog circuits,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 864-872, Nov. 1995.
[9] B. J. Blalock, P. E. Allen, and G. A. R. Rincon-Mora, “Designing 1-V Op Amps using standard digital CMOS technology,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 769-780, July 1998.
[10] T. Serrano-Gotarredona, B. Linares-Barranco, and A. G. Andreou, “A general translinear principle for subthreshold MOS transistors,” IEEE Trans. Circuits Syst. I, vol. 46, pp. 607-616, May 1999.
[11] S. S. Rajput, and S. S. Jamuar, “Low voltage, low power high performance current mirror for portable analogue and mixed mode applications,” IEE Proc.-Circ. Devices Syst., vol. 148, No. 5, pp. 273-278, Oct. 2001.
[12] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, Inc., 1997.
[13] S. S. Rajput and S. S. Jamuar, “A high performance current mirror for low voltage designs,” in Proc. APPCAS-2000, Tianjin, China, Dec. 2000, pp. 170-173.
[14] P. Hasler and T. S. Lande, “Overview of floating gate devices, circuits and systems,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 1-3, Jan. 2001.
[15] F. Munoz, A. Torralba, R. G. Carvajal, J. Tombs, and J. Ramirez- Angulo,“Floating gate biased tunable low voltage linear transconductor and its applications to filter design,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 106-110, Jan. 2001.
[16] Y. Berg, T. S. Lande, O. Naess, and H. Gundersen, “Ultra low voltage floating gate transconductance amplifiers,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 32-44, Jan. 2001.
[17] J. Ramirez-Angulo, S. C. Choi, and G. G. Altamirano, “Low voltage circuits building blocks using multiple input floating gate transistors,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 971-974, Nov. 1995.
[18] J. Mulder, A. C. van der Woerd, W.A. Serdijn, and A. H. M. van Roermund,“Application of back gate in MOS weak inversion translinear circuits,”
IEEE Trans. Circuits Syst. I, vol. 42, pp. 958-962, Nov. 1995.
[19] T. C. Huang, M. C. Huang, and K. J. Lee, “Built-in current sensor designs based on the bulk-driven technique,” in Proc. 6th ATS '97, 17-19 Nov. 1997, pp. 384-389.
[20] B. J. Blalock and P. E. Allen, “A low-voltage, bulk-driven MOSFET current mirror for CMOS technology,” in Proc. ISCAS '95, vol. 3, 30 Apr.-3 May, 1995, pp. 1972-1975.
[21] D. Y. Aksin, “A high-precision high-resolution WTA-MAX circuit of O(N) complexity,” IEEE Trans. Circuits Syst. II, vol. 49, pp. 48-53, Jan. 2002.
[22] J. A. Starzyk and Ying-Wei Jan, “A voltage based winner takes all circuit for analog neural networks,” in Proc. IEEE 39th MWSCAS, vol. 1, 18-21 Aug. 1996, pp. 501-504.
[23] N. Donckers, C. Dualibe, and M. Verleysen, “Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all, ” in Proceeding of the 7th International Conference on Microelectronics for
Neural, Fuzzy and Bio-Inspired Systems, IEEE Comput. Soc, Los Alamitos, CA, USA, 1999, pp. 360-365.
[24] A. Fish and O. Yadid-Pecht, “CMOS current/voltage mode winner-take-all circuit with spatial filtering,” in Proc. ISCAS '01, vol. 3, 6-9 May 2001, pp. 636-639.
[25] Y. C. Hung and B.D. Liu, “A CMOS vector quantizer for patter recognition,” in Proc. IEEE 1st AP-ASIC’99, Seoul, Korea, Aug. 1999, pp. 112-115.
[26] Semiconductor Industry Association. (2002). International technology roadmap for semiconductors 2002 update. [Online]. Available: http://public.itrs.net/.

校內：2006-07-08公開
校外：2006-07-08公開

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