本論文提出一種採用快速傅立葉處理器應用於逐漸趨近式類比數位轉換器之數位校正方法。此校正演算法可用來克服來自製程偏移所造成之電容不匹配，電容不匹配會造成類比數位轉換器所轉換之數位碼發生錯誤，而本論文所提出之校正方法為利用演算法分析三次諧波的量值進而求得電容實際之權重，並將原先輸出之發生錯誤之數位碼重新編碼後輸出。快速傅立葉轉換器被廣泛使用於生醫、影像處理、通訊等系統，因此利用本論文提出之校正方法對於上述系統並不會造成額外的硬體負擔。由十二位元之逐漸趨近式類比數位轉換器行為模型之模擬結果可得知，在1%之電容不匹配下，其校正後之ENOB可提高約2位元，校正後之SNDR可提高約14.52分貝。
本論文所提出之類比數位轉換器使用標準TSMC 0.18μm 1P6M製程，由量測結果可得知，在操作電壓為3.3伏特，每秒四十萬次的取樣下。在二千赫茲的輸入訊號下，經過演算法校正後所得到的訊號雜訊失真比、無雜訊影響動態範圍和有效位元數分別為66.46分貝、80.75分貝和10.75位元。電路的功率消耗為1.84毫瓦

This thesis presents a Fast-Fourier-Transform-Based calibration technique for successive-approximation-registers analog-to-digital converters (SAR ADCs). The proposed calibration technique can correct the error introduced by the capacitor mismatch, which results in the wrong output digital codes. The proposed algorithm can be adopted to evaluate the real radix of the capacitor array and generate new output digital codes to compensate the error. Since Fourier Transform analysis is widely used in biomedical, communication and image processing systems, it can be reused for calibrating SAR ADCs without increasing hardware complexity. According to the simulation result of a 12-bit SAR ADC behavior model with 1 % capacitor mismatch, the effective number of bit (ENOB) and the signal-to-noise ratio (SNDR) can be enhanced about 2 bits and 14.52 dB respectively.
The proposed SAR ADC is fabricated in TSMC 0.18μm 1P6M technology. The measurement result reveals that the SNDR, spurious free dynamic range (SFDR) and ENOB is 66.46 dB, 80.75 dB and 10.75-bit respectively after calibration, where the power supply is 3.3-V and the frequency of input signal is 2-kHz with the 400-kS/s sampling rate. The total power dissipation of the proposed ADC is 1.84 mW.

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