本論文為低溫度係數能隙參考電壓設計，內容分為兩個部分:第一部分為子電路-能隙參考電壓(Bandgap Voltage Reference )電路的設計；第二部分為完整的曲率校正能隙參考電壓電路設計。本論文中所設計的電路皆為在TSMC 0.18 μm CMOS 的製程環境下完成。
第一部分為具曲率改正( Curvature Correction )能隙參考電壓電路。利用曲率改正以及微調( Trimming ) 來降低輸出電壓的溫度變異。在-40°C ~ 120°C 的範圍內，達到低於10ppm/°C之低溫度變異的效果，晶片面積為0.664mm²。除此之外，此電路為後續研究之雛型驗證電路。
第二部分為具曲率校正( Curvature Calibration )能隙參考電壓電路，本論文提出了一個新的曲率校正方法，透過對曲率改正電路內的電流大小依據溫度區間進行校正，以消除曲率改正後的曲率殘留。其中包含一個10位元之逐次逼近暫存器型類比數位轉換器( 10-bit Successive Approximation Register ADC ) 作為溫度數位轉換器( TDC )，並用溫度所對應的校正碼來校正曲率改正電路，來對微調以及曲率改正間的干擾進行改善，進一步降低曲率的現象，以產生更精準的參考電壓。在低速且低解析度要求的情況下，使用SAR ADC 比起傳統的TDC 所使用的三角積分類比數位轉換器( Delta Sigma ADC )，在電路複雜度以及對於時鐘的要求均被大幅度地簡化且易於實現。最後模擬的結果可以達到sub-1ppm/°C的溫度係數。整體晶片面積為1760𝜇𝑚×1760𝜇𝑚，核心區域為 700𝜇𝑚×900𝜇𝑚，啟動校正電路時的功耗為 1.98mW，電路操作頻率為200kHz。

This thesis presents a low temperature-dependent variation bandgap voltage reference circuit design divided into two parts: the first part focuses on the sub-circuit design of a bandgap voltage reference (BGR), and the second part details a complete curvature calibrated bandgap voltage reference circuit. Both proposed circuits are implemented using the TSMC 0.18 μm CMOS process.
The first part introduces a bandgap voltage reference circuit with curvature correction. By utilizing curvature correction and trimming techniques, the temperature-dependent variation of the output voltage is significantly reduced. Simulation results demonstrate a low temperature coefficient (TC) of less than 10 ppm/°C across a temperature range from 40°C to 120°C. The total chip area is 0.664 mm².
The second part presents a curvature-calibrated bandgap voltage reference circuit, in which a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) operating as a Temperature-to-Digital Converter (TDC) are integrated. This configuration utilizes temperature-dependent calibration codes to calibrate the curvature correction circuit, thereby mitigating the interference between trimming and curvature correction, further suppressing the curvature effect, and generating a more precise reference voltage. For low-speed and low-resolution requirements, employing a SAR ADC as a TDC drastically simplifies circuit complexity and clock requirements compared to the traditional Delta-Sigma ADC, making it much easier to implement. The final simulation results achieve a sub-1 ppm/°C temperature coefficient. The overall chip area is 1760μm× 1760μm with a core area of 700μm× 900μm. The power consumption is 1.98 mW when the calibration circuit is activated, and the operating frequency is 200 kHz.

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