本論文以TSMC 0.25mm 1P5M CMOS製程研製2.4GHz ISM頻帶CMOS功率放大器以及單混頻器架構收發機之射頻前端CMOS RFIC。在CMOS功率放大器方面，在採用偏壓式二極體線性器架構之下，ACPR約有2.3dBc的提升(modulation: π/4 DQPSK, data rate: 48.6Kbps, channel spacing: 30kHz, channel BW: 24.3kHz)，線性增益大於11.2dB，功率增加效率(PAE)大於28%，1dB增益壓縮點大於21.2dBm。而CMOS收發機射頻前端採取單混頻器架構，中頻為280MHz，包含低雜訊放大器(LNA)、收發開關(T/R switch)、被動開關型混頻器(passive switching mixer)、驅動功率放大器(driver PA)。
CMOS收發機射頻前端整合量測結果為: 在接收模式下，轉換增益為2dB(無中頻放大器)，雜訊指數為6.2dB，input P1dB為-11dBm，在384kbps的π/4 DQPSK 調變訊號下，靈敏度為-101dBm(@BER=10-5)，動態響應範圍為90dB。由於混頻器及T/R 收發開關的損耗過大，故串接兩個驅動功率放大器以提供發射模式足夠的增益; 在發射模式下，轉換增益為7.8dB，output P1dB為11.5dBm，在輸出功率為10dBm，而頻道間隔設為384kHz時，ACPR為-32dBc，EVM值為4.1%。

This thesis presents the development of 2.4GHz ISM-band transceiver front-end CMOS RFICs and a CMOS PA using diode linearizer fabricated in TSMC 0.25μm 1P5M CMOS process. The PA has linear power gain of 11.2dB, output P1dB of 21.2dBm and PAE of 28%. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer to improve linearity. Measurement results shows 2.3dB improvement in ACPR (modulation: π/4 DQPSK, data rate: 48.6Kbps, channel spacing: 30kHz, channel BW: 24.3kHz).
The 2.4GHz transceiver front-end CMOS RFICs includes LNA、T/R switch、passive switching mixer and driver PA and the IF frequency is at 280MHz. Measured results of the 2.4GHz transceiver front-end CMOS RFIC shows as follows (with 384kbps,π/4 DQPSK modulated signal). The receiving mode has 2dB conversion gain, 6.2dB noise figure, -11dBm IIP3, –101dBm sensitivity (@BER =10-5) and 90dB dynamic range. Due to the loss of mixer and T/R switch, we use two driver PA connected in series to acquire higher gain in transmitting mode. The transmitting mode has 7.8dB conversion gain, 11.5dB output P1dB, 4.1% EVM and -32dBc ACPR (channel spacing 384kHz).

[1] SIG, Bluetooth specitfication version 1.0B, 1999.
[2] IEEE Standard 802.11b: Higher-Speed Physical Layer Extension in the 2.4GHz Band.
[3] IEEE Standard 802.11a: High-Speed Physical Layer in the 5GHz Band.
[4] T. Yoshimasu, M. Akagi, N. Tanba, and S. Hara, “An HBT MMIC Power Amplifier with an Integrated Diode Linearizer for Low-Voltage Portable Phone Applications,” IEEE J. of Solid-State Circuits, vol. 33, NO. 9, Sep. 1998.
[5] T. Yoshimasu, M. Akagi, N. Tanba, and S. Hara, “A low distortion and high efficiency HBT MMIC power amplifier with a novel linearization technique forπ/4 DQPSK modulator,” IEEE GaAs IC Symp. Tech. Dig. 1997, pp. 45-48.
[6] S.-Y. Liu and H.-R. Chuang, “2.4 GHz Transceiver RF Front-end for ISM-Band Digital Wireless Communications,” Applied Microwave and Wireless, pp. 32-48, June 1998.
[7] TSMC, TSMC 0.25um mixed signal 1P5M+ salicide 2.5/3.3V RF spice models, 2001.
[8] CIC教育訓練課程，RF CMOS Design Flow，民國八十九年。
[9] Behzad Razavi, RF Microelectronics, Prentice-Hall, Inc., 1998.
[10] Steve C. Cripps, RF Power Amplifier for Wireless Communications, Artech House, 1999.
[11] G. Hau, T. B. Nishimura and N. Iwata, “A Highly Efficient Linearized Wide-Band CDMA Handset Power Amplifier Based on Predistortion Under Various Bias Conditions,” IEEE Trans. on Microwave Theory Tech., vol. 49, pp.1194-1201, June 2001.
[12] B. Kim, J. S. Ko and K. Lee, “A New Linearization Technique for MOSFET RF Amplifier Using Multiple Gated Transistors,” IEEE Microwave and Guided Wave Letters, vol. 10, NO.9, September 2000.
[13] K. Yamauchi, K. Mori, M. Nakayama, Y. Itoh and ect, “A Novel Series Diode Linearizer for Mobile Radio Power Amplifiers,” Microwave Symposium Digest, vol.2, pp. 831-834, 1996.
[14] K. Yamauchi, K. Mori, M. Nakayama, Y. Mitsui, T. Takagi, “Microwave Miniaturized linearizer Using A Parallel Diode,” Microwave Symposium Digest, vol.3, pp. 1199-1202.
[15] T. Yoshimasu, M. Akagi, N. Tanba and S. Hara, “An HBT MMIC Power Amplifier with an Integrated Diode Linearizer for Low-Voltage Portable Phone Application”, IEEE J. of Solid-State Circuits, Vol. 33, No. 9, pp. 1290-1296, 1998.
[16] Peter B. Kenington, High-Linearity RF Amplifier Design, Artech House, 2000.
[17] D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997.
[18] C. Y. Cha and S. G. Lee,“A Low Power, High Gain LNA Topology,” Int. Microwave and Millimeter Wave Technology conf., pp. 420~423, 2000.
[19] H. Samavati, H. R. Rategh and T. H. Lee, “A 5-GHz CMOS Wireless Lan Receiver Front End,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765-772, May 2000.
[20] H. Hashemi and A. Hajimiri, “Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 288-301, Jan. 2002.
[21] OKI Technical Review, GaAs AGC Amplifier for CDMA Cellular Phone Systems, number.158, vol.63, April 1997.
[22] 林昂生，應用在數位音訊廣播(DAB)接收機L頻帶降頻器之CMOS單晶射頻微波積體電路，國立成功大學電機工程學系碩士論文，民國九十年。
[23] A. R. Shahani, D. K. Shaeffer and T. H. Lee, “A 12-mW Wide Dynamic Range CMOS Front-End for a Portable GPS Receiver,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2061-2070, Dec. 1997.
[24] F. J. Huang, and O, “A 0.5-mm CMOS T/R Switch for 900-MHz Wireless Applications,” IEEE J. of Solid-State Circuits, Vol. 36, No. 3, pp. 486-492, March 2001.
[25] K. Yamamoto, et. al., “A 2.4-GHz-Band 1.8-V Operation Single-Chip Si-CMOS T/R-MMIC Front-End with a Low Insertion Loss Switch,” IEEE J. of Solid-State Circuits, Vol. 36, No. 8, pp. 1186-1197, August 2001.
[26] D. M. Pozar, Microwave Engineering, Addison-Wesley, 1990.
[27] C. Wang, L. E. Larson and P. M. Asbeck, “A Nonlinear Capacitance Cancellation Technique and its Application to a CMOS Class AB Power Amplifier,” IEEE RFIC Symposium Digest, pp. 39-42, 2001.
[28] Philips Semiconductor, Philips RF/Wireless Communications Data Handbook, 1996