隨著科技演進，智慧水表產品問世，水流速的量測，可以利用時間至數位轉換器的技術，監測是否有漏水的現象，近幾年使用的時間轉數位轉換的電路，大多都是以游標尺延遲線(Vernier Delay Line)，或是搭配其他校準方式提升解析度，但犧牲量測範圍或是增加功率消耗，另外也有客製化(Full-Custom)的方式，以電晶體層級(transistor level)設計邏輯閘能有更好的效能，但需要花更長的時間設計。
本論文提出可合成時間數位轉換器架構，藉由二維延遲串(delay chain)產生隨機相位插值，可以讓相位平均分布 (Uniform Distribution)，減少非線性的問題。此架構在40nm CMOS的製程，在不需額外校準電路的情況下，可以維持在1.96ps的解析度，且在相同製程下，比一維隨機相位插值方法減少17%功耗下，DNL也改善4.7%。

As the rapid development of technology, ultrasonic flow meters can measure water flow by Time-to-Digital Converters (TDC) and detect whether there is leak in the pipe. In recent years, most of TDC designs are based on Vernier delay line(VDL) or integrate with different calibration methods to improve the resolution, but decrease dynamic range or increase power consumption. In addition, the use of the full-custom design flow can redesign logic gate in transistor level to solve these problems, but consume more time.
We proposed a synthesizable TDC architecture using a two dimensional delay chain to generate stochastic phase interpolation. The stochastic phase can be uniform distribution to improve the non-linearity problem. The proposed algorithm can achieve resolution of 1.96ps using 40nm process and reduces power consumption by 17% when compared to one dimensional stochastic phase interpolation with 4.7% DNL improvement.

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