1687標準又稱IJTAG，定義了基於序列掃描且具彈性的架構，可以有效率地存取晶片內部的電路。本篇論文提出一創新的架構，結合1687標準以及ㄧ有效率的測試控制器來執行三維積體電路的自動化測試。此測試控制器能傳送平行的測試資料至1687標準之架構以及待測試電路，並提供所需的控制訊號以控制整個測試流程。這個設計能達到全速度、自動化及可程式化的三維積體電路測試。在實驗結果中，在考量這個設計之自動化測試的能力的情況下，這個設計的額外面積負擔及測試時間負擔是很小的。

IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this thesis, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.

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