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研究生：	邱敏瑞 Chiu, Min-Jui
論文名稱：	具抑制碼相關電源電流干擾之十四位元每秒兩百億次取樣數位類比轉換器 A 14-bit 20GS/s DAC with Code-Dependent Supply Current Interference Suppression
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2022
畢業學年度：	110
語文別：	英文
論文頁數：	113
中文關鍵詞：	數位類比轉換器、電源電流補償技術、碼相關性電源電流、電流汲取式
外文關鍵詞：	Digital-to-analog converter, supply current compensation, code-dependent supply current, Current-steering
相關次數：	點閱：102 下載：0
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因應新世代通訊應用蓬勃發展，通訊積體電路的需求大幅度地上升且需具備快速及準確處理大量資料的能力。為達到上述需求，在通訊系統中的發射器需要一具備高速操作能力的高解析電流汲取式數位類比轉換器(DAC)。而針對現代化行動及衛星通訊規格，本論文中實作兩個具有奈奎式及超越奈奎式模式的高速高解析數位類比轉換器來分別涵蓋其所需的頻帶。
第一個晶片實現一個十四位元5.2GS/s之電流汲取式數位類比轉換器。在如此高速操作下，DAC的輸出線性度會受限於電流源不匹配、切換突波效應、有限輸出阻抗與碼相關性電源電流等非線性問題。為抑制由非線性問題導致的失真，本論文對該DAC採用二元隨機選擇技術、同心平行四邊形繞線、切換突波補償償及輸出阻抗補償來改善輸出的線性度。另外，為克服碼相關性電源電流效應，本論文提出電源電流補償技術來補償代碼轉換期間DAC的電源電流。因此，由於碼相關性電源電流所導致的碼相關性電源抖動可被抑制，故改善DAC輸出的線性度。相較於現有解決方法，電源電流補償技術於高速DAC中具有較少功耗與面積。最後，本論文採用電阻回授反向器來縮短所需的安定時間並抑制符碼間干擾，以利突破邏輯電路的切換速度限制，可緩解製程對於實現高速數位類比轉換器的限制。此DAC已使用台積電40nm製程工藝實現，且有源面積約為0.16mm2。根據量測結果，在整個第一耐奎斯特頻帶中，數位類比轉換器的無雜散動態範圍(SFDR)分別於低頻輸出及高頻輸出為70.3dBc及63.3dBc。在整個第二耐奎斯特頻帶中，數位類比轉換器的SFDR分別於低頻輸出及高頻輸出為58.4dBc及42.4dBc。與現有頂尖文獻之≥6-bit及≥2GS/s 40nm數位類比轉換器量測相比，品質因數達到世界最佳之壯舉，可適用於行動通訊應用，例如: 4G LTE、5G sub-6GHz及藍牙等。
第二個晶片則是沿襲第一個晶片之線性化技術，並實現一個十四位元20GS/s之電流汲取式數位類比轉換器，可支援0至20GHz訊號輸出。為提升操作速度，此晶片採用新穎的分裂式同心平行四邊形繞線佈局與具有斬波器的高速切換驅動器，並使用兩倍分時式架構實現數位碼產生器，以利降低所需推動負載且縮短資料及時脈路徑之繞線長度，且減少20GS/s DAC所需的功耗及面積。此晶片預計使用台積電40nm製程工藝製作，有源面積約為0.1mm2。根據全晶片後佈局模擬結果，不同製程變異下的數位類比轉換器輸出無雜散動態範圍分別於第一個耐奎斯特頻帶及第二個耐奎斯特頻帶可達到>58dBc及>50dBc。相比現有≥10-bit及≥6GS/s的數位類比轉換器，此DAC於fout等於10GHz時具有9dBc改善量，且於SFDR 等於 61dBc 時提升1.2倍的fout。預計晶片製作完成後，SFDR量測結果將超越現有頂尖文獻，因此更適用更多下世代行動通訊及衛星通訊等應用。

As advanced communication applications develop sustainably, the demand for communication ICs, which need to process large amounts of data quickly and accurately, is increasing vastly. To fulfill the above requirements, the high-resolution current-steering digital-to-analog converter (DAC), which has the ability for high-speed operations, is required for transmitters in the communication system. For specifications of modern mobile and satellite communication, this thesis implements two DAC ICs with Nyquist mode and over-Nyquist mode to cover their required bandwidths, respectively.
The first IC realizes a 14-bit 5.2GS/s current-steering DAC. For the high-speed operation, the output linearity of such a DAC is limited to non-linear problems, such as the mismatch of current sources, switching glitch effect, and finite output impedance. To suppress the distortion induced by these non-linear problems, this thesis adopts the random-rotated based selection (RRBS), concentric parallelogram routing (CPR), switching-glitch compensation (SGC), and output impedance compensation (OIC) for this DAC. Furthermore, to overcome the code-dependent supply current effect, which seriously degrades the DAC linearity, a supply current compensation (SCC) is proposed in this thesis to compensate for the current of the DAC’s supply during the code transition. As a result, the code-dependent supply bouncing induced by the code-dependent supply current is suppressed, thus improving the linearity of the DAC output. Compared to prior-art solutions, the SCC has less power, area, and complexity for the high-speed DAC. Finally, this DAC adopts resistive-feedback inverters to shorten the required settling time, thus suppressing the ISI error and overcoming the transition-speed limitation of logic circuits. As a result, it relaxes the process limitation to realize the high-speed DAC. This DAC has been fabricated in TSMC’s 40nm process with a 0.16mm2 active area. According to the measurement result, for the entire first Nyquist band, the spurious-free-dynamic range (SFDR) of the DAC with a low-frequency output (low fout) and a high-frequency output (high fout) are 70.3dBc and 63.3dBc, respectively. For the entire second Nyquist band, the SFDR of the DAC with a low fout output and a high fout are 58.4dBc and 42.4dBc, respectively. Compared to the measurements of state of the art ≥6-bit and ≥2GS/s 40nm DACs, this DAC has the best figure of merit (FoM), thus being suitable for mobile communications, such as 4G LTE, 5G sub-6GHz, and Bluetooth.
The second IC adopts the linearization techniques of the first chip and realizes a 14-bit 20GS/s current-steering DAC with a 0.1mm2 active area, which can support output signals with 0-20GHz. To enhance the operation speed, this chip adopts the novel split concentric parallelogram routing (SCPR), high-speed switch drivers with choppers, and the 2X time-interleaved digital code generator to alleviate the required driving loading and shorten the routing length of the data and clock paths, thus decreasing the required power and area of the DAC. This chip is expected to be fabricated in TSMC’s 40nm process with a 0.1mm2 active area. According to the result of the whole-chip post-layout simulation, the DAC analog output achieves >58dBc SFDR in the first Nyquist band and >51dBc SFDR in the second Nyquist band under different process corners. Compared to state of the art ≥10-bit and ≥6GS/s DACs, this DAC achieves a 9-dB better SFDR with fout equal to 10 GHz, and a 1.2x higher fout with an SFDR equal to 61dBc. After this chip has been fabricated as expected, the measured SFDR will surpass the state of the art. Therefore, it is suitable for many next-generation mobile and satellite communication systems.

Abstract (Chinese)	I
Abstract (English)	III
Acknowledgement	V
Table of Contents	VI
List of Tables	VIII
List of Figures	IX
Chapter1 Motivation and Introduction of DAC	1
1 Motivation	1
2 Introduction and Prior-Art DAC Architecture	4
2.1 Resistor-Based DAC	5
2.2 Switching-Capacitor DAC	6
2.3 Current-Steering DAC	6
3 Performance Index of DAC	8
3.1 Static Performance	8
3.2 Dynamic Performance	12
4 Nyquist and Over-Nyquist DAC	15
5 Organization	17
Chapter2 Non-Linear Problems and Used Linearization Techniques	18
1 Random Mismatch Effect of Current Sources	18
1.1 Introduction	18
1.2 Comparison of Prior-Art Solution for Random Mismatch	19
1.3 Random-Rotated Based Selection (RRBS)	22
2 Gradient Mismatch Effect of Current Sources	24
2.1 Introduction	24
2.2 Comparison of Prior-Art Layout Arrangement	25
2.3 Split Concentric Parallelogram Routing (SCPR)	30
3 Glitch-Induced Non-Linearity of Current Sources	31
3.1 Introduction	31
3.2 Switching-Glitch Compensation (SGC)	35
4 Speed Limitation of Logic Circuits in High-Speed DAC	37
4.1 Introduction	37
4.2 Resistive-Feedback Inverter	38
5 Finite Output Impedance	40
5.1 Introduction	40
5.2 Output Impedance Compensation (OIC)	42
Chapter3 Proposed Supply Current Compensation (SCC)	45
1 Introduction of Code-Dependent Supply Current	45
1.1 Source of Unit Supply Current	46
1.2 Supply Current Effect of 1-bit DAC	47
1.3 Supply Current Effect of N-bit DAC	48
2 Prior-Art Solutions and SCC Motivation	51
2.1 Code-Independent Supply Current	51
2.2 Supply Impedance Reduction	53
2.3 SCC Motivation	59
3 SCC for High-Speed DACs	59
3.1 Introduction	60
3.2 Concept and Operation	60
3.3 Circuit Implementation	64
4 Simulated Result of DAC with SCC	70
Chapter4 1st chip – 14-bit 5.2GS/s DAC for Mobile Communication	73
1 Analog Output Generator 	74
1.1 Current Cell Array with CPR	75
1.2 High-Speed Switch Driver and Retiming DFF	78
1.3 LVDS and Clock-Tree Circuit	80
1.4 On-Chip Distributed Analog LDO	82
2 Digital-Code Generator	82
2.1 SGC Code Generator	82
2.2 RRBS Circuit	84
2.3 Series-In Parallel-Out FIFO	85
3 Layout Floor Plan and Whole-Chip Layout	87
4 Whole-Chip Measurement	89
4.1 Measurement Setup 	89
4.2 PCB Design 	91
4.3 Measurement Results	92
Chapter5 2nd chip – 14-bit 20GS/s DAC for Satellite Communication	95
1 Analog Output Generator 	96
1.1 Current Cell Array with SCPR	96
1.2 High-Speed Switch Driver with Chopper and Retiming DFF	98
2 Time-Interleaved Digital-Code Generator	99
2.1 Frequency Divider 	100
2.2 Serializer 	100
3 Layout Floor Plan and Whole-Chip Layout	101
4 Whole-Chip Simulation	103
4.1 Pre-Layout Simulation	103
4.2 Post-Layout Simulation 	104
5 Expected Measurement	108
Chapter6 Conclusion and Future Work	109
1 Conclusion	109
2 Future Work	110
Reference	111
                                    

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