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研究生： 梁嘉偉
Liang, Jia-Wei
論文名稱： 高產出平行化AVC/H.264內文適應性二位元算數解碼器
A High Throughput Parallel AVC/H.264 Context-Based Adaptive Binary Arithmetic Decoder
指導教授： 李國君
Lee, Gwo-Giun
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 64
中文關鍵詞： 內文適應性二位元算數解碼 、平行化 、Viterbi解碼器 、資料流
外文關鍵詞： CABAC, parallelization, Viterbi decoder, dataflow
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    • 基於對二位元算數解碼之平行化技術，本論文提出了一個具高產出特色之AVC/H.264 平行化內文適應性二位元算數解碼器。依據由上而下之設計方法，分析演算法和分別於高階層及低階層做資料流模型為設計架構之步驟。基於演算法分析，找出了內文適應性二位元算數解碼器與Viterbi解碼器之相似度，並藉以展開二位元算數解碼之平行度。藉由增加二位元算數解碼之平行度，本論文所提出架構之產出比起循序之 bin 解碼要高了3.5 倍，且於108MHz的時脈下，每秒所解出之bin個數達到378M。此設計之規格是針對AVC/H.264 High Profile，4.2 Level，解析度1920x1088及畫面更新率每秒64 張。

    In this thesis, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder with high throughput is proposed. Based on the top-down design methodology, algorithm analyzing and dataflow modeling in both high and low granularities are performed to achieve the proposed architecture. According to the analysis for algorithm, the similarity between CABAC decoder and Viterbi decoder is found to extend the degree of parallelism for binary arithmetic decoding. The application of proposed design is specified to support AVC/H.264 High Profile, 4.2 Level, and 1920x1088 resolution at 64 frames per second. By increasing the degree of parallelism of bin decoding, the throughput of the proposed architecture is shown by the experiments to have improved 3.5 times as compared to the sequential bin decoding, and the decoded bin per second can reach 378M at clock speed 108MHz.

    Abstract ii Table of Contents iii List of Tables vi List of Figures vii Chapter 1 Introduction 1 1.1 Video Coding 1 1.2 AVC/H.264 Video Coding Standard 2 1.2.1 Context-based Adaptive Binary Arithmetic Coding (CABAC) 4 1.3 Reconfigurable Video Coding (RVC) 4 1.3.1 MPEG-2 Video Coding Standard 5 1.4 Organization of this Thesis 6 Chapter 2 Reconfigurable Video Coding Decoder 7 2.1 Introduction to RVC Decoder 7 2.2 RVC Decoder Specification 7 2.3 High Level Data Flow Model 8 2.4 Low Level Data Flow Model 8 2.5 Parser Module in RVC Decoder 10 2.5.1 The Hardware Parsing Processor 10 2.5.2 The Embedded CPU 10 2.6 CABAC Module in RVC Decoder 11 Chapter 3 Overview for the Algorithm of CABAC 12 3.1 Introduction to Entropy Coding 12 3.1.1 Self-Information 12 3.1.2 Huffman Coding 13 3.1.3 Arithmetic Coding 13 3.2 Entropy Coding in AVC/H.264 14 3.3 The Block Diagram of CABAC 14 3.4 The Flowchart of CABAC 16 3.5 Binarization Types in CABAC 18 3.5.1 Unary Binarization 18 3.5.2 Truncated Unary Binarization 19 3.5.3 Concatenated Unary/k-th Order Exp-Golomb Binarization 19 3.5.4 Huffman Binarization 21 3.5.5 Fixed-length Binarization 24 3.5.6 Fixed-length/truncated unary Binarization 24 3.5.7 Signed Exp-Golomb Coding/unary Binarization 24 3.6 Context-based Probability Model 25 3.6.1 Context Information 25 3.6.2 Probability Model 26 3.7 Binary Arithmetic Decoding 29 3.7.1 Renormalization 29 3.7.2 Regular Binary Arithmetic Decoding 30 3.7.3 Bypass Binary Arithmetic Decoding 31 3.7.4 Termination Binary Arithmetic Decoding 32 3.8 The Arrangement for CABAC Decoding 33 Chapter 4 Proposed Architecture of CABAC Decoder 34 4.1 The Limited Throughput of CABAC 34 4.2 Analysis for Worst Case of Bin Number 35 4.3 The Parallelism in Viterbi Decoder 35 4.4 Parallel Scheme for Bin Decoder 37 4.5 The Analysis for the Distribution of Symbols 40 4.6 High Level Data Flow for CABAC Decoder 43 4.7 Low Level Data Flow for CABAC Decoder 50 4.7.1 Refinement for CABAC Module 53 4.8 Proposed Architecture of CABAC Decoder 53 Chapter 5 Experimental Result and Verification 57 5.1 Experimental Result 57 5.2 Verification 58 5.2.1 Verification for High Level Data Flow Model 59 5.2.2 Verification for Low Level Data Flow Model 60 5.2.3 Verification for Register Transfer Level Model 60 Chapter 6 Conclusion and Future Work 61 6.1 Conclusion 61 6.2 Future Work 62 Reference 63

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    [2] ITU-T Recommendation H.264, “Advanced video coding for generic audiovisual services,” Draft, Mar. 2005.
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    [10] H.264/AVC reference software JM16.2, http://iphome.hhi.de/suehring/tml/.
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    [12] ITU-T H.264.1 “Conformance specification for H.264 advanced video coding”, Mar. 2005.
    [13] Recommendation ITU-R BT.656-4, “Interfaces for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at The 4:2:2 Level of Recommendation ITU-R BT.601 (Part A)”, 1998.
    [14] Yao-Chang Yang and Jiun-In Guo, “A High Throughput H.264/AVC High Profile CABAC Decoder for HDTV Applications,” IEEE Transactions on Circuits and Systems for Video Technology, Volume 19, Issue 9, pp. 1395-1399, Sep. 2009.
    [15] Pin-Chih Lin, Tzu-Der Chuang, and Liang-Gee Chen, “A Branch Selection Multi-symbol High Throughput CABAC Decoder Architecture for H.264/AVC, ” IEEE International Symposium on Circuits and Systems, pp. 365-368, May 2009.
    [16] Peng Zhang, Don Xie, and Wen Gao, “Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Issue 3, pp. 417-426, Mar. 2009.

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