本論文提出一個支援類比數位轉換器內建式自我測試電路之單晶片系統測試平臺用以解決嵌入式類比數位轉換器的測試問題。其主要原理在於藉由內建於單晶片系統中的處理器作為測試控制核心，並執行一測試程式控制整個測試流程。此測試程式係經由一處理器可控制之內建式自我測試電路的輔助進而掌控整個類比數位轉換器的測試流程。經由處理器適當的控制設定自我測試電路內部的控制器，此平台可提供在不同頻率下類比數位轉換器的效能參數量測能力。此項量測是經由弦波統計的技術而完成，並可據此而得類比數位轉換器的偏移誤差、倍率誤差、整體非線性誤差及差分非線性誤差等參數。結合本實驗室已完成的另一成果，本測試平台可同時支援已加入標準(boundary scan or IEEE P1500)週邊掃瞄電路等測試輔助電路的數位核心電路之測試與嵌入式類比數位轉換器的測試。最後實驗結果顯示所提出的單晶片系統測試平臺能有效的完成類比數位轉換器的測試，且能大量降低晶片整體的測試成本。

This thesis presents a system-on-a-chip (SOC) test platform supporting analog-to digital converter (ADC) built-in self-test (BIST) to solve the embedded ADC test problem. An embedded processor in the platform is employed as a test control kernel to execute a test program. The program handles the testing of the ADCs cores in the SOC with the assistance of a processor-controlled BIST circuit. The platform provides a parametric measurement capability at different frequencies via properly settling the BIST controller using the embedded processor. The parameters of the ADC cores, including offset, gain, integral nonlinearity (INL) and differential nonlinearity (DNL) error, are tested via a sinusoidal histogram technique. Combined with the previous work developed in our lab, a complete SOC test platform supporting the testing of digital cores wrapped by the standardized boundary scan wrappers or the IEEE P1500 wrappers and the testing of the ADC cores is developed. The results show that the proposed SOC test platform is efficient and can greatly reduce the total test cost of an SOC chip.

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