本論文為應用於5G無線通訊之3.5 GHz 頻段下的整數型鎖相迴路電路設計，內容可分為兩個部分：第一部分為鎖相迴路的其中一個子電路，壓控振盪器的設計；第二部分為完整的整數型鎖相迴路。在本論文所設計之兩個電路皆使用 TSMC 0.18 µm CMOS製程設計實現。
在第一部分壓控振盪器採用可調式電容陣列並加入開關方式提高容值變化範圍，進而使壓控振盪器的頻率可調範圍增加。在本次設計電路之量測頻率變化範圍為3.42 GHz~3.83 GHz (11.3%)。
相位雜訊在頻率偏移 1 MHz處的最佳表現為 -126.4 dBc/Hz；整體輸出功率皆大於 5 dBm；功率消耗為 21.3 mW。包含緩衝放大器之整體晶片面積為1.055 mm^2。
在第二部分3.5 GHz整數型鎖相迴路中，子電路包含相位頻率偵測器(PFD)、充電泵(CP)、迴路低通濾波器(LPF)、壓控振盪器(VCO)、除頻器(divider)。在本次設計電路之量測參考頻率為109.375 MHz，操作頻率為3.42 GHz ~ 3.83 GHz；相位雜訊在頻率偏移 1 MHz處的最佳表現為 -93 dBc/Hz，整體皆小於-85 dBc/Hz；輸出功率皆落在0 dBm；整體功率消耗為31.7 mW。包含緩衝放大器之整體晶片面積為1.982 mm^2。

This thesis is a circuit design for the signal source of wireless communication chips in the frequency band near 3.5 GHz in 5G. It is divided into two parts: the first part is a P-type LC voltage-controlled oscillator using a capacitor array, the second part is a 3.5 GHz integer phase-locked loop circuit design. The above mentioned circuit is realized by TSMC 0.18 µm CMOS process, and the supply voltage is 1.8 V.
The first part of the voltage-controlled oscillator with the capacitor array can greatly increase the adjustable frequency range from the original (no capacitor array) 4.6% to 11.3%. It enables the phase-locked loop to be locked under various frequency bands. The frequency band above 200 MHz is enough for the phase-locked loop. The best performance of phase noise at 1 MHz offset from 3.7 GHz is -126.4 dBc/Hz. the power consumption is 21.3mW. The total chip size including the buffer amplifier and the bonding pads is 1.055 mm^2.
The second part is the 3.5 GHz integer PLL design, the sub-circuits include phase frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO), and frequency divider (divider). The output power of the phase-locked loop measurement results has dropped to about 0dBm, but it is still about 60dBm larger than the noise floor. The 1 MHz-offset overall phase noise is -90.33 dBc/Hz at 3.52 GHz and -93 dBc/Hz at 3.84 GHz, which is within a reasonable range. The reference frequency of this design is 109.375 MHz, which corresponds to an output frequency of 3.5 GHz. The power consumption of the overall PLL is 31.7 mW. The total chip size including the buffer amplifier and the bonding pads is 1.982 mm^2.

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