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研究生： 邱凱增
Chiou, Kai-Tzeng
論文名稱： 高速快閃式類比數位轉換器的速度強化技巧
Speed Enhancement Technique for High-Speed Flash Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 82
中文關鍵詞： 類比數位轉換器 、速度強化技巧 、前置放大器 、快閃式類比數位轉換器
外文關鍵詞： analog-to-digital converter, speed enhancement technique, preamplifier, flash ADC
相關次數： 點閱：83  下載：7 
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    • 本論文提出一個具有速度強化技術之快閃式類比數位轉換器。量化器是快閃式類比數位轉換器的核心電路之一，通常是由一級或數級前置放大器與比較器所組成，其中前置放大器影響系統頻寬甚鉅，因此前置放大器的設計經常是決定快閃式類比數位轉換器能否高速操作的關鍵元件。本論文提出一個速度強化的前置放大器，並結合管線式訊號處理的技巧，實現一個高速四位元快閃式類比數位轉換器。
    本論文所研製的快閃式類比數位轉換器採用台灣積體電路公司90-nm 1P9M CMOS製程進行設計，晶片面積為0.03 mm2。實測結果顯示，在每秒取樣三十三億次的情況下其有效位元數可達 3.81-bit，當輸入頻率為1550 MHz時有效位元數可達 3.32-bit，其有效解析頻寬非常接近尼奎式頻率。量測的微分非線性誤差與積分非線性誤差方面分別為 -0.29/0.46 LSB 與 -0.26/0.20 LSB。在1伏特於取樣率為三十三億次的情況下整體的功率消耗為76.87毫瓦。

    A high-speed flash analog-to-digital converter (ADC) with speed enhancement technique is proposed in this thesis. In a flash ADC, quantizer is one of the major building blocks, and generally consists of several stages of preamplifiers and a regenerative latch comparator. The preamplifier is the critical component to achieve high-speed operation because the system bandwidth is usually determined by preamplifiers. This thesis proposes a speed-enhancing preamplifier and manipulates a wave-pipeline technique to implement a high-speed 4-bit flash ADC.
    The proposed ADC is fabricated in TSMC 90-nm 1P9M CMOS process and occupies 0.03 mm2 active area. The measurement results show that the ADC achieves an ENOB of 3.81-bit at 3.3-GS/s. When the input frequency is 1550 MHz, the ENOB is 3.32-bit. The effective resolution bandwidth is nearly Nyquist frequency. The measured DNL and INL are within -0.29/0.46 LSB and -0.26/0.20 LSB, respectively. The total power dissipation is about 76.87-mW from a 1-V supply at 3.3-GS/s.

    Table of Contents VI List of Figures VII List of Tables XI Chapter 1 Introduction 1 1.1 INTRODUCTION AND MOTIVATION 1 1.2 ORGANIZATION 4 Chapter 2 Basics of Analog-to-Digital Converters 5 2.1 ADC ARCHIRECTURE 5 2.2.1 Flash ADC 5 2.2.1.1 Reference Ladder 8 2.2.1.2 Track and Hold Circuit 10 2.2.1.3 Comparator 13 2.2.1.3 Digital Encoder 17 2.2.2 Two-Step ADC 20 2.2.3 Successive Approximation ADC 21 2.2.4 Pipelined ADC 22 2.2 DESIGN TECHNIQUES FOR FLASH ADC 24 2.2.1 Averaging Technique 24 2.2.1.1 Resistive Averaging 27 2.2.1.2 Active Averaging 28 2.2.2 Interpolation Technique 29 2.2.1.1 Resisitive Interoplation 29 2.2.1.2 Active Interpolation 30 2.3 RECENT HIGH-SPEED FLASH ADCS 31 2.3.1 10 GSamples/s, 4-bit, 1.2V, Design-for-Testability ADC and DAC in 0.13μm CMOS technology 31 2.3.2 A 4-bit 10GSample/sec Flash ADC with Merged Interpolation and Reference Voltage 32 2.3.3 A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS 33 2.3.4 A 43mW Single-Channel 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS 35 2.3.5 A 5-GS/s 4-Bit Flash ADC with Triode-Load Bias Voltage Trimming Offset Calibration in 65-nm CMOS 36 2.3.6 A 4-bit 12GS/s Data Acquisition System-on-Chip Including a Flash ADC and 4-Channel DeMUX in 130 nm CMOS 37 Chapter 3 Design of the High-Speed Flash ADC 38 3.1 PROPOSED ARCHITECTURE 38 3.2 SPEED-ENCHANING PREAMPIFIER 39 3.2.1 Conventional Preamplifier 39 3.2.2 Speed Enhancement Technique 44 3.3 CIRCUIT IMPLEMENTATION 51 3.3.1 Comparator 51 3.3.2 Thermometer Code to Gary Code Encoder 52 3.3.3 Gary Code to Binary Code Encoder 56 3.3.4 Down-Sampler 57 3.4 LAYOUT AND FLOOR PLAN 58 Chapter 4 Simulation and Measurment Results 62 4.1 SIMULATION RESULTS 62 4.2 MEASURMENT RESULTS 70 4.2.1 Measurment Environment 70 4.2.2 Measured Results 72 Chapter 5 Conclusions and Future Work 76 Bibliography 78

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