在超寬頻系統中，類比至數位轉換器的效能與功率消耗對整體系統的效率具有重要的影響。本論文著重高速類比至數位轉換器的設計考量，並提出一個應用於超寬頻系統之六位元快閃式類比至數位轉換器的設計。這個設計使用所提出的前置放大器設計方法，可在給定功率的情況下達到最高的頻寬，並且利用所提出比較器的時脈改進方法來降低電路的非理想性。此外，本電路使用偏移消除、電容式插補、以及分散式取樣和維持技巧以解決在快閃式類比至數位轉換器設計上遭遇的問題。本設計使用台積電 0.13 微米製程實現。晶片實際量測結果顯示，在七億赫茲的取樣頻率下，有效位元數為五點三位元。消耗功率為一百一十二毫瓦，有效解析度頻寬為五億赫茲。由於高輸入頻寬以及低功率消耗，本論文中所提出之電路相當適合應用於超寬頻系統。

The performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of the ultra wideband (UWB) systems. In this thesis, we focus on the design techniques development of high speed ADCs, and propose a 6-bit high speed ADC design for the applications of UWB systems. In this design, a design methodology for pre-amplifier is used to achieve the maximum bandwidth while consuming the fixed power. Also, the non-ideality of comparators can be suppressed by improving the comparator’s timing. This proposed design adopts the offset cancellation, capacitive interpolation and distributed sample-and-hold techniques to solve the problems in designing flash ADCs. This proposed ADC is designed in TSMC 0.13m process, and the experimental results show that the effective number of bit (ENOB) is 5.3 in the sampling frequency of 700MHz. The power consumption is 112mW, and the resolution bandwidth (ERBW) is 500MHz. Due to the high input bandwidth and low power consumption, this ADC is very suitable to UWB systems.

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