隨著超大型積體電路製程的快速進步，單一的晶片裡能夠整合的電晶體數量愈來愈多，這使得擁有高效能、縮短設計時程及降低製造成本等多項優點的單晶片系統成為一項非常有吸引力的設計方法。單晶片系統通常會使用一個或多個一般應用或特殊設計的處理器核心，然而，單晶片系統環境下貧乏的可控制性和可觀察性，造成測試處理器核心的工作變得相當困難，傳統上測試處理器的方法是利用以掃描鏈為基礎的設計，但這樣的設計將會對於電路面積和速度造成很大的影響，而且也很難用處理器所使用的頻率做為測試的頻率；若以電路面積和速度做為重要考量的情形下，僅僅使用指令和資料做為測試向量的功能性測試 (functional testing) 就是一個不錯的測試方法了。因此本論文提出一個混合了手寫產生和亂數產生測試程式的功能性測試方法，來解決測試嵌入式處理器核心的問題。

為了驗證該測試方法的效果，我們使用了一個ARM9處理器作為測試樣本。實驗結果顯示出該方法提供了一個可行的途徑用以解決嵌入式處理器的測試問題。

With rapidly advanced VLSI manufacturing technology, it is possible to have an enormous number of transistors on a single die. These technology advances make system-on-chip (SOC) with shorter time-to-market, higher performance and lower manufacturing cost becoming an attractive solution in the IC design industry. SOCs usually have one or more general or special purpose processors. However, it is difficult to test these embedded processors because of the poor controllability and observability in SOC environment. Traditional scan-based testing for embedded processors will result in not only area overhead but also performance impact, and it is difficult to implement at-speed testing. Functional testing which uses only the instructions and data as test patterns is a good solution when area and performance are critical. In this thesis, a method which mixes manual and random test programs to functionally test the embedded processor is developed.

To verify the practicability of the method, we use an ARM9 processor as the benchmark. Experimental results show the proposed method is a good solution for embedded processor test problems.

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