本論文分為兩個部分，第一部分為應用於 5G 通訊中 2.4-GHz 之低電壓、低功耗以及低雜訊壓控振盪器設計，第二部分為應用於鑽石結構中氮空位量子感測器之2.87-GHz 次取樣鎖相迴路設計。在本論文中所設計之電路皆使用 TSMC 0.18μm CMOS 製程進行下線並完成量測。
在第一部分中透過電流再利用技術設計振盪器，使得操作直流電流同時流經NMOS 和 PMOS 電晶體。相較於傳統差動式振盪器而言，此方法在較低的功耗下，擁有相近的 gm 值，使得電流再利用型壓控振盪器適合應用在低功耗的環境下。同時，相對在功耗減半的情況下，相位雜訊效能還能達到與傳統壓控振盪器同樣的水準表現。然而，電流再利用型壓控振盪器有著明顯的缺陷，就是架構上的不對稱，導致輸出振幅會有誤差存在。而本論文利用自發轉導匹配技術(Spontaneous Transconductance Matching Technique)，使用電感中央抽頭來感測並回授振幅誤差給可變電阻級的電晶體，使可變電阻可動態調變壓控振盪器轉導級，使輸出振幅誤差減少、振幅不對稱的情況得以改善。電流再利用型壓控振盪器還有另一項缺點，就是對於製程以及電壓的變異非常敏感。而本次設計提出基極偏壓技術，使用此技術搭配自發轉導匹配技術，利用中央抽頭端的回授信號回授給壓控振盪器轉導級的基極端，使電晶體的臨界電壓可動態調整，降低製程以及電壓變異的影響。量測結果顯示，可調頻率範圍為 11.81%，可調頻率範圍從 2.23-GHz 至 2.51-GHz。功率消耗為 1.2 mW，相位雜訊在頻率偏移1-MHz 處表現為-119.8 dBc/Hz，整體輸出功率皆大於-7.22 dBm，面積為 0.948 mm²。本設計之壓控振盪器 FoM 為-186.6 dB。
第二部分為 2.87-GHz 之次取樣鎖相迴路設計。與傳統整數型鎖相迴路相比，次取樣鎖相迴路利用次取樣技術，可以消除除頻器帶來的雜訊乘以 N²倍的影響。但是，由於次取樣相位偵測器頻率獲取範圍有限，故需要鎖頻迴路幫助迴路鎖定，為了不影響次取樣鎖相迴路輸出，在鎖頻迴路的相位頻率偵測器後加上兩個 D 型正反器，產生出死區，在相位差小於半參考週期時，鎖頻迴路停止運作，而此時次取樣鎖相迴路由主要迴路鎖定，以此達到消除除頻器影響的目的。在本電路量測中，參考信號頻率設定為 89.6875-MHz，量測其輸出頻率為 2.87-GHz，符合本次設計需求。相位雜訊在頻率偏移 1-MHz處表現為-92.8 dBc/Hz、時脈抖動為 1.975 ps，輸出功率為 0.569 dBm，Reference Spur Level 為-62.289 dBc。整體次取樣鎖相迴路消耗功率為 12 mW，面積為1.67 mm²，本次設計之次取樣鎖相迴路 FoM 為-223.3 dB。

This thesis is divided into two parts. The first part focuses on the design of a low-voltage, low-power and low-noise 2.4-GHz voltage-controlled oscillator (VCO) for 5G communications. The second part covers the design of a 2.87-GHz sub-sampling phase-locked loop (PLL) for nitrogen-vacancy's quantum sensors in diamond structures. Both circuits in this thesis are implemented by TSMC 0.18 μm CMOS process.
In the first part, a current-reuse technique is employed in the oscillator design, reducing the DC current flowing through the VCO to half that of a conventional VCO, making the current-reuse VCO suitable for low-power environments. Despite the reduced power consumption, the phase noise performance remains comparable to that of traditional VCOs. However, a major drawback of the current-reuse VCO is its asymmetric structure, which leads to output amplitude errors. To address this, a spontaneous transconductance matching technique is introduced, using a center-tapped inductor and feedback signal from the tap node to a variable resistor. This allows the dynamic adjustment of the VCO's transconductance stage, thereby reducing output amplitude errors and improving the symmetry of the amplitude. Another drawback of the current-reuse VCO is its sensitivity to process and voltage variation. To mitigate this drawback, a body biasing technique is proposed, combined with the spontaneous transconductance matching technique. Feedback signal from the tap node is used to dynamically adjust the transistor's threshold voltage, reducing the impact of process and voltage variations. Measurement results show that the VCO has a tuning range from 2.23 GHz to 2.51 GHz, tuning range is 11.81%. The measured phase noise is -119.8 dBc/Hz at 1-MHz offset. The output power is greater than -7.22 dBm. Core circuit's power consumption is 1.2 mW. Chip area is 0.948 mm². The figure of merit (FoM) for the VCO is -186.6 dB.
The second part presents the design of a 2.87-GHz subsampling PLL. Compared to traditional integer-N PLLs, the subsampling PLL eliminates the noise multiplication by a factor of N² caused by the frequency divider through subsampling techniques. However, the limited frequency acquisition range of the subsampling phase detector requires a frequency-locked loop (FLL) to assist in locking the loop. To prevent the FLL from affecting the subsampling PLL output, two D-type flip-flops are added after the phase frequency detector of the FLL to create a dead zone. When the phase error is less than half of the reference cycle, the FLL stops operation, allowing the subsampling PLL to lock via the main loop and effectively eliminate the impact of the frequency divider. In the measurement, a reference signal frequency is set to 89.6875 MHz, the output frequency is measured at 2.87 GHz, meeting the design requirements. The phase noise is -92.8 dBc/Hz at 1-MHz offset, jitter is 1.975 ps, output power is 0.569 dBm, and the reference spur level is -62.289 dBc. The overall power consumption of the sub-sampling PLL is 12 mW, with a chip area of 1.67 mm². The figure of merit (FoM) for the sub-sampling PLL is -223.3 dB.

[1] 國家實驗研究院，科普講堂 -5G 真 的 有 這 麼 好 嗎 ? ，https://www.narlabs.org.tw/xcscience/cont?xsmsid=0I148638629329404252&sid=0K195427304270721566
[2] 國家實驗研究院，科普講堂 - 量 子 電 腦 的 原 理 、 挑 戰 與 未 來 衝 擊 ，https://www.narlabs.org.tw/xcscience/cont?xsmsid=0I148638629329404252&sid=0M103505917643100370&sq=%E9%87%8F%E5%AD%90%E9%9B%BB%E8%85%A6
[3] L. Childress, R. Hanson, "Diamond NV centers for quantum computing and quantum networks," MRS Bulletin, Vol. 38, pp. 134-138, Feb. 2013.
[4] M. I. Ibrahim, C. Foy, D. Kim, D. R. Englund and R. Han, "Room-Temperature Quantum Sensing in CMOS: On-Chip Detection of Electronic Spin States in Diamond Color Centers for Magnetometry," IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, Jun. 2018, pp. 249-250.
[5] D. Kim, M. I. Ibrahim, C. Foy, M. E. Trusheim, R. Han, and D. R. Englund, "CMOS-Integrated Diamond Nitrogen-Vacancy Quantum Sensor," Nature Electronics, Vol. 2, pp. 284-289, Mar. 2019.
[6] S. -J. Yun, S. -B. Shin, H. -C. Choi and S. -G. Lee, "A 1mW current-reuse CMOS differential LC-VCO with low phase noise," IEEE International Digest of Technical Papers. Solid-State Circuits Conference, San Francisco, CA, USA, Vol. 1, pp. 540-616, Feb. 2005.
[7] J. P. Hong, S. J. Yun, N. J. Oh and S. G. Lee, "A 2.2-mW Backgate Coupled LC Quadrature VCO With Current Reused Structure," IEEE Microwave and Wireless Components Letters, vol. 17, no. 4, pp. 298-300, Apr 2007.
[8] W. Ying, P. Qin, J. Jin and T. Mo, "A 1mW 5GHz current reuse CMOS VCO with low phase noise and balanced differential outputs," International Symposium on Integrated Circuits, Singapore, 2011, pp. 543-546.
[9] C. -L. Yang and Y. -C. Chiang, "Low Phase-Noise and Low-Power CMOS VCO Constructed in Current-Reused Configuration," IEEE Microwave and Wireless Components Letters, vol. 18, no. 2, pp. 136-138, Feb. 2008.
[10] M. -D. Wei, S. -F. Chang and S. -W. Huang, "An Amplitude-Balanced CurrentReused CMOS VCO Using Spontaneous Transconductance Match Technique," IEEE Microwave and Wireless Components Letters, vol. 19, no. 6, pp. 395-397, Jun. 2009.
[11] Z. Wang, H. S. Savci, J. Griggs and N. S. Dogan, "1-V Ultra-Low-Power CMOS LC VCO with Dynamic Body Biasing," International Symposium on Signals, Circuits and Systems, Iasi, Romania, Jul. 2007, pp. 1-4.
[12] J. -Y. Hsieh and H. -C. Kuo, "A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology," IEEE Microwave and Wireless Components Letters, vol. 32, no. 4, pp. 324-326, Apr. 2022.
[13] G. H. Tan, H. Ramiah, P. -I. Mak and R. P. Martins, "A 0.35-V 520-μW 2.4-GHz Current-Bleeding Mixer With Inductive-Gate and Forward-Body Bias, Achieving >13-dB Conversion Gain and >55-dB Port-to-Port Isolation," IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 4, pp. 1284-1293, Apr. 2017.
[14] T. Azadmousavi, E. N. Aghdam and J. Frounchi, "A Low Power Current-Reuse LC-VCO with Self Body-Bias Schema," Iranian Conference on Electrical Engineering (ICEE), Mashhad, Iran, May 2018, pp. 294-299.
[15] F. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980.
[16] T. -H. Lin, C. -L. Ti and Y. -H. Liu, "Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- $N$ PLLs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 877-885, May 2009.
[17] C. -F. Liang, S. -H. Chen and S. -I. Liu, "A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems," IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 390-398, Feb. 2008.
[18] S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, "A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation," IEEE Journal of Solid-State Circuits, vol. 48, no. 5, pp. 1151-1160, May 2013.
[19] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, "A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N²," IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.
[20] K. K. Hung, P. K. Ko, C. Hu and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Transactions on Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990.
[21] D. B. Leeson, "A simple model of feedback oscillator noise spectrum," Proceedings of the IEEE, vol. 54, no. 2, pp. 329-330, Feb. 1966.
[22] Z. Zong, G. Mangraviti and P. Wambacq, "Low 1/f3 Noise Corner LC-VCO Design Using Flicker Noise Filtering Technique in 22nm FD-SOI," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 5, pp. 1469-1480, May 2020.
[23] B. Razavi, RF Microelectronics. Second edition, Prentice Hall, Inc., 2012.
[24] D. Wu, R. Huang, W. Wong and Y. Wang, "A 0.4-V Low Noise Amplifier Using Forward Body Bias Technology for 5 GHz Application," IEEE Microwave and Wireless Components Letters, vol. 17, no. 7, pp. 543-545, Jul. 2007.
[25] G. H. Tan, R. M. Sidek and M. M. Isa, "Design of ultra-low voltage and low-power CMOS current bleeding mixer," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Ishigaki, Japan, Nov. 2014, pp. 344-347.
[26] J. -Y. Hsieh and K. -Y. Lin, "A 0.7-mW LC Voltage-Controlled Oscillator Leveraging Switched Biasing Technique for Low Phase Noise," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 8, pp. 1307-1310, Aug. 2019.
[27] W. -C. Lai, S. -L. Jang, B. -S. Shih and Y. -J. Su, "Low power class-C VCO using dynamic body biasing," International Symposium on Next Generation Electronics (ISNE), Keelung, Taiwan, May 2017, pp. 1-4.
[28] Wen-Kuan Yeh, Shuo-Mao Chen and Yean-Kuen Fang, "Substrate noise-coupling characterization and efficient suppression in CMOS technology," IEEE Transactions on Electron Devices, vol. 51, no. 5, pp. 817-819, May 2004.
[29] N. R. Sivaraaj and K. K. A. Majeed, "A Comparative Study of Ring VCO and LC-VCO: Design, Performance Analysis, and Future Trends," IEEE Access, vol. 11, pp. 127987-128017, Nov. 2023.
[30] 劉深淵(作)、楊清淵(譯)，鎖相迴路，滄海書局，2006.
[31] Behzad Razavi, Design of CMOS Phase-Locked Loops : From Circuit Level To Architecture Level, Cambridge University Press, 2020.
[32] X. Gao, E. Klumperink and B. Nauta, "Sub-sampling PLL techniques," IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, Sept. 2015, pp. 1-8.
[33] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts and B. Nauta, "Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 117-121, Feb. 2009.
[34] X. Gao, E. A. M. Klumperink, G. Socci, M. Bohsali and B. Nauta, "Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector," IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sept. 2010.
[35] N. Hemapradhap and J. Ajayan, "High speed low-power true single-phase clock divide-by-16/17 dual-modulus prescaler using 130nm CMOS process with a Vdd of 1.2V," International Conference on Circuit, Power and Computing Technologies (ICCPCT), Nagercoil, India, Mar. 2016, pp. 1-6.
[36] S. Tooprakai and A. Tudsorn, "A 1.2 V low-power true single-phase clock CMOS 2/3 prescalers," International Conference on Information Science, Electronics and Electrical Engineering, Sapporo, Japan, Apr. 2014, pp. 1691-1694.
[37] Z. Tibenszky, M. Kreißig, C. Carta and F. Ellinger, "A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment," IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 4, pp. 2236-2245, Apr. 2022.
[38] X. Ding, J. Wu and C. Chen, "A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 202-206, Feb. 2019.
[39] C. Wan, T. Xu, X. Yi and Q. Xue, "A Current-Reused VCO With Inductive-Transformer Feedback Technique," IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 5, pp. 2680-2689, May 2022.
[40] Z. Xing, H. Liu, Y. Wu, C. Zhao, Y. Yu and K. Kang, "A 3-GHz Inverse-Coupled Current-Reuse VCO Implemented by 1:1 Transformer," IEEE Microwave and Wireless Components Letters, vol. 32, no. 5, pp. 434-436, May 2022.
[41] K. -W. Cheng, S. -K. Chang and Y. -C. Huang, "Low-Power and Low-Phase-Noise Gm-Enhanced Current-Reuse Differential Colpitts VCO," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 5, pp. 733-737, May 2019.
[42] D. Liao, F. F. Dai, B. Nauta and E. A. M. Klumperink, "A 2.4-GHz 16-Phase SubSampling Fractional-N PLL With Robust Soft Loop Switching," IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 715-727, Mar. 2018.
[43] Y. C. Qian, Y. Y. Chao and S. I. Liu, "A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 269-273, Feb. 2022.
[44] D. Liao, Y. Zhang, F. F. Dai, Z. Chen and Y. Wang, "An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO," IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 536-546, Mar. 2020.
[45] Y. Choi et al., "A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 7, pp. 2734-2743, Jul. 2023.