成功大學博碩士論文系統

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研究生：	林進富 Lin, Jin-Fu
論文名稱：	使用修正時間位移式相關重複取樣電路技巧之高速管路式類比數位轉換器 A High Speed Pipelined A/D Converter Using Modified Time-Shifted CDS Technique
指導教授：	張順志 Chang, Soon-Jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	119
中文關鍵詞：	數位-類比轉換器、相關重複取樣、管路式、資料轉換器
外文關鍵詞：	pipeline, data converter, Analog-to-digital converter(DAC), correlated double sampling (CDS)
相關次數：	點閱：95 下載：9
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　　隨著製程技術的演進，基於可靠度的考量，低電壓操作已經變成未來電路的趨勢，然而電路的供應電壓不斷的下降的同時，將會減少電路的信號動態範圍。若欲維持一定的動態範圍，必須設法抑制雜訊並降低訊號失真量，如此將間接增加類比電路的功率消耗。在傳統管路式類比數位轉換器的設計中，需要一個極高增益的運算放大器來確保訊號處理的準確性，而製程的限制將使這樣的運算放大器的設計面臨極大的困難。在這邊我們提出一個名叫修正時間位移式相關重複取樣的電路技巧來克服需要高增益運算放大器所帶來的種種實現上的困難。我們使用台積電0.18微米互補式金氧半製程並搭配所提出的電路技巧來設計一個10位元每秒取樣100萬次的管路式類比數位轉換器。此晶片的操作電壓為1.8伏特而其面積為2 mm2，其功率消耗為100 mW。
　　除了晶片設計之外，在本論文中，我們利用Simulink 工具來建立一個完整的管路式類比數位轉換器的高階系統行為模型，此模型包含許多實際電路將會存在的非理想效應，我們可利用此模型進行電路效能的預測，以減少電路的設計時間，除此之外，我們亦可利用此模型在系統層級進行電路功率消耗的最佳化。

　With the advance of deep submicron technology, the low power supply will become the trend of circuit development based on the consideration of circuit reliability. However, the signal dynamic range will be decreased as the reduction of supply voltage. In order to restore the dynamic range, we must suppress the noise and signal distortion. By this way, it will indirectly increase the power consumption of analog circuits. Especially, a high-gain op-amp must be required to guarantee the required accuracy in the conventional pipelined ADC design. However, due to the process limitations, it is difficult to implement such high-gain op-amp. The penalty of additional power dissipation must be usually paid to implement this op-amp. In this thesis, a technique called as modified time-shifted CDS is proposed to relax the requirement of high-gain op-amp in the pipelined ADC design. A 10-bit 100 MS/s pipelined A/D converter has been designed and implemented with the TSMC 0.18 m CMOS 1P6M process. The power consumption of this chip is 100mW at 1.8 V, and the chip area is 2 mm2.
　In addition to the chip design of pipelined ADC, a complete behavioral model including many non-idealities is constructed by Simulink tool. This model can be used to predict the performance of pipelined ADC, which can reduce the design time significantly. In addition, we can use this model to optimize power consumption of a pipelined ADC in behavior level.

                             Table of Contents

Abstract …………………………………………………………………………I
Acknowledgment …………………………………………………………………V
Table of Content ………………………………………………………………VII
List of Tables …………………………………………………………………XI
List of Figures…………………………………………………………………XII

Chapter 1 Introduction…………………………………………………………1
1 Motivation……………………………………………………………………1
2 Thesis Organization ………………………………………………………4
Chapter 2 Analog-to-Digital Converte r……………………………………6
1 Concepts of ADC Conversion	……………………………………………6
1.1 Classification and Transformation of Signals……………………6
1.2 Sampling Theorem of the A/D Conversion	………………………8
2 Review of High Speed ADCs Architecture	………………………10
2.1 Flash ADC	…………………………………………………………………11
2.2 Two-Step ADC	………………………………………………………12
2.3 Pipelined ADC	………………………………………………………15
2.4 Comparison among ADC Architectures	………………………16
3 ADCs Performance Metrics	……………………………………………18
3.1 Static Specifications	……………………………………………18
3.1.1 Resolution	………………………………………………………18
3.1.2 Offset Error	………………………………………………………18
3.1.3 Gain Error	………………………………………………………19
3.1.4 Nonlinearity	………………………………………………………19
3.1.5 Accuracy	………………………………………………………20
3.2 Dynamic Specifications	……………………………………………21
3.2.1 Signal-to-Noise Ratio	……………………………………………21
3.2.2 Signal-to-Noise and Distortion Ratio	………………………23
3.2.3 Spurious-Free Dynamic Range	…………………………………23
3.2.4 Dynamic Range	………………………………………………………24
3.2.5 Input Bandwidth	………………………………………………………24
4 Summary ………………………………………………………………………25
Chapter 3  System Design of High Speed Pipelined ADC…………………26
1 Introduction…………………………………………………………………26
2 Key Building Blocks of Pipelined ADCs ………………………………27
3 Digital Error Correction Technique……………………………………31
4 Considerations about Stage Resolutions in Pipelined ADCs………36
5 Behavioral Model of Pipelined ADCs……………………………………38
5.1 Ideal Model of Pipelined ADC…………………………………………38
5.2 Non-idealities in Pipelined ADCs……………………………………44
5.2.1 The non-idealities about Op-Amp …………………………………44
5.2.2 The non-idealities about Switches ………………………………52
5.2.3 Clock Jitter……………………………………………………………56
5.3 Complete Behavioral Model of Pipelined ADCs with Non-linearities……57
5.4 Simulation Results………………………………………………………59
6 Stage Accuracy Requirement………………………………………………61
6.1 Accuracy Requirement of Each Pipelined Stage……………………61
6.2 Considerations about Capacitor Value in Switched -Capacitor Circuits…62
6.3 Required OP-Amp Specifications………………………………………64
6.4 Design Example……………………………………………………………67
7 Summary	…………………………………………………………………70
Chapter 4  The Implementation of Proposed High Speed Pipelined ADC………71
1 Introduction…………………………………………………………………71
2 Conventional Time-Shifted CDS Technique ……………………………72
3 Proposed modified Time-Shifted CDS Technique………………………79
3.1 Operational Principal …………………………………………………79
3.2 Behavioral Model and Simulation Results	………………………82
4 Circuit Design and Implementation ……………………………………85
4.1 Operational Amplifier …………………………………………………86
4.1.1 Circuit Description …………………………………………………86
4.1.2 Simulation Results……………………………………………………89
4.2 Front-End Sample and Hold Circuit	…………………………………91
4.3 MDAC with Time-Shifted CDS Technique………………………………94
4.4 Implementation of Bootstrapped Switch……………………………96
4.5 Dynamic Comparator and Sub-ADCs……………………………………98
4.6 Clock Generator	……………………………………………………101
5 Simulation Results of the Proposed Pipelined ADC………………105
6 Layout and Floor Plan	…………………………………………108
7 Summary	………………………………………………………………110
Chapter 5  Conclusions and Future Work…………………………………111
1 Conclusions	………………………………………………………………111
2 Future Work	………………………………………………………………112

Reference…………………………………………………………………………113
 

                                    

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校內：2007-08-15公開
校外：2008-08-15公開

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