在CMOS數位電路中，大部分的消耗功率以動態功率為主。根據動態消耗功率的公式可以得知減少消耗功率最有效的方法之一，就是降低電路的操作電壓。然而，任意的調降電壓會使得電路的操作速度變慢，最後導致系統的執行效能變差。因此，本論文提出一種啟發式的配置方法，針對在邏輯閘層次上，利用多重電壓配置技術的概念，來達到減少消耗功率的目的。在配置的演算法中內建對元件時序與功率分析的功能，增加演算法在驗證過程中的便利性與完整性。
實驗結果顯示，在不違反時序限制的條件下，本論文提出的方法對於不同的測試電路，可以減少的消耗功率最高可達53.6%。

The majority of power consumption in CMOS digital circuits is dynamic power. According to the formula of dynamic power consumption, one of the most effective techniques to reduce power consumption is supply voltage reduction. However, reducing supply voltage without further consideration could also result in performance degradation of the system. Therefore, we have proposed a heuristic assignment algorithm which used multiple supply voltage techniques to achieve power reduction at gate level. We had also embedded the timing and power analysis functions into the assignment algorithm which could enhance the convenience and the integrity in the verification process. Experimental results show that the proposed algorithm can reduce power consumption up to 53.6% without timing violation for various benchmark circuits.

[1] Power consumption for various technologies. [Online]. Available: http://www.intel.com
[2] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS", IEEE Journal of Solid-State Circuits, vol. 30, issue 8, pp. 847-854, Aug. 1995.
[3] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits", IEEE Journal of Solid-State Circuits, vol. 32, issue 6, pp. 861-869, June 1997.
[4] T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme", IEEE Journal of Solid-State Circuits, vol. 31, issue 11, pp. 1770-1779, Feb. 1996.
[5] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits", IEEE Proceedings, vol. 91, issue 2, pp. 305-327, Feb. 2003.
[6] W. Liqiong, C. Zhanping, M. Johnson, K. Roy, and V. De, "Design and optimization of low voltage high performance dual threshold CMOS circuits", in Proceedings of the 35th annual conference on Design automation, pp.489-494, June 1998.
[7] H. Zhigang, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose, "Microarchitectural Techniques for Power Gating of Execution Units", in Proceedings of International Symposium on Low Power Electronics and Design, pp. 32-37, Aug. 2004.
[8] K. H. Ock and S. Youngsoo, "Analysis and optimization of gate leakage current of power gating circuits", in Proceedings of the 2006 conference on Asia South Pacific design automation, pp. 565-569, Jan. 2006.
[9] U. Kimiyoshi and H. Mark, "Clustered voltage scaling technique for low-power design", in Proceedings of the 1995 international symposium on Low power design Dana Point, California, United States, pp. 23-26, April 1995.
[10] K. Usami, T. Ishikawa, M. Kanazawa, and H. Kotani, "Low-power design technique for ASICs by partially reducing supply voltage", in Proceedings 9th Ann. IEEE Int. ASIC Conf. and Exhibit, Rochester, New York, pp.301-304, Sept. 1996.
[11] M. Igarashi, K. Usami, K. Nogami, F. Minami, Y. Kawasaki, T. Aoki, M. Takano, S. Sonoda, M. Ichida, and N. Hatanaka, "A low-power design method using multiple supply voltages", IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 36-41, Aug. 1997.
[12] K. Usami, K. Nogami, M. Igarashi, F. Minami, Y. Kawasaki, T. Ishikawa, M. Kanazawa, T. Aoki, M. Takano, C. Mizuno, M. Ichida, S. Sonoda, M. Takahashi, and N. Hatanaka, "Automated low-power technique exploiting multiple supply voltages applied to a media processor", IEEE Custom Integrated Circuits Conf., pp.131-134, March 1997.
[13] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa, M. Ichida, and K. Nogami, "Automated low-power technique exploiting multiple supply voltages applied to a media processor", IEEE Journal of Solid-State Circuits, vol. 33, issue 3, pp. 463-472, March 1998.
[14] J. Y. Jou and D. S. Chou, "Sensitisable-path-oriented clustered voltage scaling technique for low power", in IEE Proceedings of Computers and Digital Techniques, vol. 145, pp. 301-307, July 1998.
[15] K. Usami and M. Igarashi, "Low-power design methodology and applications utilizing dual supply voltages", in Proceedings of the Asia and South Pacific Design Automation Conference 2000, pp 123-128, January 2000.
[16] D. Monica, M. Luca, M. Alberto, M. Enrico, and P. Massimo, "Enhanced clustered voltage scaling for low power", in Proceedings of the 12th ACM Great Lakes symposium on VLSI New York, New York, USA, pp. 18-19, April 2002.
[17] S. H. Kulkarni, A. N. Srivastava, and D. Sylvester, "A new algorithm for improved VDD assignment in low power dual VDD systems", in Proceedings of International Symposium on Low Power Design, pp. 200-205, Aug. 2004.
[18] P. Padmanabhan and G. S. Kang, "Real-time dynamic voltage scaling for low-power embedded operating systems", in Proceedings of the eighteenth ACM symposium on Operating systems principles Banff, Alberta, Canada, pp. 21-24, October 2001.
[19] Design Compiler v.2004.12, Synopsys Inc.
[20] PrimeTime v.2003.12, Synopsys Inc.
[21] PrimePower v.2003.12, Synopsys Inc.
[22] Library Compiler User Guide: Modeling Timing and Power Technology Libraries. Synopsys Online Documentation, 2004.
[23] PrimeTime User Guide: Fundamentals. Synopsys Online Documentation, 2004.
[24] CIC eNEWS vol.36 & vol.46. [Online]. Available: http://www.cic.org.tw
[25] Y. F. Chiu, J. S. Guo and L. C. Cheng, "Advanced Gate Level Model Survey and Research," in SoC Technology Center, 2006.
[26] ISCAS Benchmarks. [Online]. Available: http://www.fm.vslib.cz/~kes/asic/iscas/
[27] 2004 IC/CAD Contest [Online]. Available: http://www.ee.ncu.edu.tw/~cad_contest/
[28] 2006 IC/CAD Contest [Online]. Available: http://www.ee.ncu.edu.tw/~cad_contest/