| 研究生: |
吳盈澂 Wu, Ying-Cheng |
|---|---|
| 論文名稱: |
使用超取樣調變技術之伏安式恆電位儀晶片設計 Design of Voltammetry Potentiostat with Oversampling Modulation Technique |
| 指導教授: |
劉濱達
Liu, Bin-Da |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2011 |
| 畢業學年度: | 99 |
| 語文別: | 英文 |
| 論文頁數: | 72 |
| 中文關鍵詞: | 增量型類比數位轉換器 、延伸計數技術 、三角積分調變器 、伏安式恆電位儀 |
| 外文關鍵詞: | Incremental analog-to-digital converter, extended-counting technique, sigma-delta modulator, voltammetry potentiostat |
| 相關次數: | 點閱:72 下載:4 |
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本論文實現生醫感測之伏安式恆電位儀晶片設計,此晶片可應用於電化學感測器的信號處理系統,系統組成元件包含三大部分:控制定電位放大器、類比數位轉換器和微型處理控制器。根據量測感測器的電流變化量,來得知待測液中特定成份的濃度。本文採用了增量型和具有取樣電容之逐漸趨近式類比數位轉換器,獲得較高電路的準確度和線性度,來降低整體功率消耗,提升電路效能。電路以TSMC 0.35 μm 2P4M製程模擬設計,使用供應電壓為5.0 V,當此轉換器操作於38.5 kHz取樣頻率時,SNDR為73.1 dB,消耗功率為2.6 mW。
另一方面,本文進一步採用超取樣調變技術來實現一個三階三位元的三角積分調變器,透過運算放大器共享技術和雙重積分技巧,來降低整體功率損耗。此架構僅使用一運算放大器即可以達到三階雜訊塑形效果,電路以TSMC 0.18 μm 1P6M製程模擬設計,使用供應電壓為1.8 V,當此調變器操作於40 kHz頻寬訊號、50倍超取樣率時,SNDR為88.5 dB,消耗功率為1.4 mW。本研究技術在低成本與低功率消耗的目標下,設計出一個可以應用於生醫感測器之伏安式恆電位儀,有效的降低生化感測晶片的成本。
In this thesis, a voltammetry potentiostat, consisting of a control amplifier, an analog-to-digital converter and a microprocessor, is presented for the signal processing of electrochemical biosensors. By measuring the results of direct current which represents redox species in the electrolyte, we can detect the concentration of analytic solution. Since biomedical applications usually have the feature of weak signals, an analog-to-digital converter using the oversampling modulation technique is proposed to achieve low offset and noise.
For the target of biomedical applications, an incremental analog-to-digital converter and a successive approximation analog-to-digital converter containing the sampling capacitors are used to achieve high efficiency and meanwhile reduce the op-amp loading. The proposed analog-to-digital converter is simulated in a 0.35 μm 2P4M 5.0 V CMOS technology. From the simulation results, the 73.1 dB SNDR is achieved with 2.6 mW total power consumption and 38.5 kHz conversion rate.
The oversampling ratio is limited by the input signal bandwidth while increasing the oversampling ratio to improve the resolution. Therefore, the number of order increased is used to achieve the high accuracy and linearity, and the op-amp sharing and double integrator technique are used to obtain a power efficient modulator and to achieve the third-order noise shaping with only one opamp. The proposed sigma-delta modultaor is simulated in a 0.18 μm 1P6M 1.8 V CMOS technology. From the simulation results, the 88.5 dB SNDR is achieved with 1.4 mW total power consumption under 50-X oversampling ratio.
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