立體視覺深度計算演算法，藉由特徵點比對獲取物體深度資訊，隨著演算法不同決定了絕大部分深度計算的準確性。本論文選擇了以常見的半全域比對演算法，結合方塊BT法的匹配成本計算來進行硬體實現，本論文中稱為半全域方塊比對演算法。在半全域比對演算法實現採取了以systolic-array為基礎，進行平行化設計來達成硬體加速的目的。在實現方塊匹配成本時，為了配合以systolic-array為基礎設計之半全域比對演算法且能有效降低記憶體存取次數，本論文提出有效重複輸入資料使用方式的FIFO Buffer，使得在一次像素運算中僅需讀取記憶體1次大幅提升運算速度。
採取平行化及重複使用輸入資料的方式，使得半全域方塊比對演算法硬體可以快速獲得深度結果。在本論文中，使用了Xilinx Virtex-5系列的FPGA做實現，硬體合成後時脈最高可達86.845 MHz。一秒鐘可計算出56張深度圖，以搜尋距離大小為64計算一張 像素大小的影像。

Stereo matching disparity estimations rely on matching costs for computing the correlation of two images. Stereo algorithms determine the most accuracy of the depth calculation. This paper is performed using semi-global matching (SGM) and blocking sampling-insensitive calculation of Birchfield and Tomasi (BT) to implementations. The algorithm is called semi-global blocking matching (SGBM) in this paper. Implementation of the SGM is a systolic-array-based, and highly parallel hardware algorithm for speeding up. In the implementation of blocking matching cost with systolic-array-based design semi-global blocking matching (SGBM) and can effectively reduce the memory access. This paper proposes A FIFO Buffer which effectively reuses input data. This technique makes per pixel operation read memory once, and then the computing speed is enhanced significantly.
Using parallel hardware and reusing input data make the semi-global block matching algorithm can quickly obtain disparity map. In this paper, an FPGA implement on Xilinx Vertex 5. The clock rate can achieve 86.845 MHz. The SGBM hardware can generate 56 fps disparity maps of image ( pixel) with the 64 search range.

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