隨著科技的進步，積體電路正朝著高性能運算（HPC）的方向發展，包括高頻傳輸速度、整合多種功能以及低功耗或高效能…等特性。因此IC的設計結構和封裝型式也逐步朝異質整合的方向轉變。但IC內電子元件和互連的密度不斷提高，IC的尺寸以及線寬、間距也相應縮小，摩爾定律的發展難以為繼，縮小晶圓製程節點正面臨物理極限和研發時間成本的消耗，所以封裝型式、技術對功能的高整合度和效能提升至關重要。本研究透過文獻回顧與專家討論，將先進封裝型式分類為3D、2.5D、扇出型晶圓級封裝以及其他新型式，透過半導體IPC分類與11位專家問卷調查的方式蒐集關鍵字，從中華民國專利資訊檢索系統，進行專利檢索，針對我國公告2012年至2022年專利作樣本分析。研究結果顯示，先進封裝型式相關專利數量於2016年達到高峰，並從2017年開始下降，說明特定技術處於成熟期走向衰退階段；技術功效矩陣分析中，3D堆疊對應體積縮小方面具高度集中，顯示此為先進封裝型式專利的匯集區，並根據專利樣本的引證次數統計出31件關鍵專利，研究結果提供相關企業作技術的研發與發展策略的考量。

With the advancement in technology, integrated circuits are trending towards high performance computing (HPC) development, including high frequency transmission speed, integration of multiple functions, and features like low power consumption or high efficiency. As a result, the IC structure design and packaging types have gradually shifted towards heterogeneous integration. However, as the density of electronic components and interconnects within the IC increases, the IC size and line width/spacing also shrink accordingly based on Moore's law. Since further scaling down of process nodes faces physical and economic limitations, packaging technologies become crucial to achieve greater integration and performance enhancement.
Advanced packaging can be categorized into 3D, 2.5D, fan-out wafer level packaging, and other emerging technologies. The purpose of this thesis is to analyze the patent maps of advanced IC packaging types in Taiwan over the past decade (2012-2022), examine the technology trends and life cycles, identify the core patents based on citation analysis, and provide suggestions on future R&D strategies.
A total of 8,708 patents were retrieved from the Taiwan patent database using relevant IPC classifications and keywords provided by industry experts. The results show that the number of advanced packaging patents peaked around 2016 and has been declining since 2017, indicating a mature stage going into decline. Patent maps illustrate that 3D stacking has the highest concentration corresponding to miniaturization. Citation analysis also reveals 31 core patents with high citations each, mostly related to through silicon via, micro bumping, and other 3D/2.5D integration technologies.

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