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研究生： 陳世綸
Chen, Shih-Lun
論文名稱： 用於單晶片網路之可重新架構處理矽核設計
Reconfigurable Processor Core Design for Network-on-a-Chip
指導教授： 周哲民
Jou, Jer-Min
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 126
中文關鍵詞： 處理器 、網路單晶片 、可重新架構
外文關鍵詞： processor, NoC, reconfigurable
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    • 　　設計一個複雜的SoC系統將會面臨許多挑戰，網路單晶片提供了一個發展平台，讓設計者實現多樣的運用於平台上。經過數個處理器架構的模擬與比較，擁有可重新架構設計的十六個運算單元處理器被選出作為本篇論文之設計。與網路介面、網路和路由器相結合，便完成了一個單晶片網路；相同的方法，一個網路晶片網可利用數個網路單晶片、網路介面、網路與路由器相互結合而成。透過階層式資料流對映，一個非常大的應用可以被階層式地對映到網路晶片網上，相較於傳統電路，此將更強大、 有彈性、可伸縮、重覆使用與可重新架構，並且對於特殊應用俱有極高的效能。

    　　To design a complex System-on-a-Chip (SoC) poses many challenges. The Network-on-a-Chip (NoC) provides designers a develop platform, on which they could implement various applications. After comparing and simulating several architectures of processor, the sixteen function-units processor with reconfigurable design is chosen for designing of this thesis. To combine with network interface, interconnection network, and routers, a NoC is complete. In the same way, a NoC mesh would be combined by several NoCs, network interface, interconnection network, and routers. Through hierarchical dataflow mapping, a very large special application could be mapped into a NoC mesh hierarchically. It would be more powerful, flexible, scalable, reusable and reconfigurable than traditional circuits and very high performance for special application.

    Abstract Chinese Abstract English Content List of figures List of tables Chapter 1 INTRODUCTION 1.1 Network on a Chip…………………………………………………2 1.2 Reconfigurable Processor Orientation………………………3 1.3 Simulation before Design………………………………………3 1.4 Thesis organization………………………………………………5 Chapter 2 Network on a Chip 2.1 Components of NoC…………………………………………………7 2.2 Communication Structure of NoC ………………………………8 2.2.1 Communication Componets……………………………………10 2.2.2 Router……………………………………………………………………12 2.3 Multiprocessor structure of NoC……………………………13 2.4 Platform Principle of NoC……………………………………16 2.4.1 The Platform-Based Design Flow……………………………16 2.4.2 Proposed NoC platform-based design………………………19 Chapter 3 Reconfigurable Principle and Application 3.1 Fine-grained Reconfigurable Architectures………………22 3.2 Coarse-grained Reconfigurable Architectures……………23 3.2.1 Mesh-Based Architectures……………………………………23 3.2.2 Based on Linear Array Architectures……………………28 3.2.3 Crossbar-Based Architectures………………………………29 3.2.4 Comparing with fine-grained………………………………30 3.3 Static Reconfiguration…………………………………………31 3.4 Dynamic Reconfiguration………………………………………31 3.5 The Reconfiguration Hierarchy………………………………32 3.5.1 Reconfiguration Vertical Axis……………………………32 3.5.2 Reconfiguration Horizontal Axis…………………………33 3.5.3 Reconfiguration Time Axis…………………………………34 Chapter 4 Polymorphous TRIPS Architecture 4.1 Granularity of parallel processing elements on a chip………………………37 4.2 Grid Processor Architectures…………………………………38 4.3 Grid Processor Execution Model………………………………41 4.4 Polymorphous TRIPS Architecture……………………………43 4.4.1 Overview of TRIPS Architecture……………………………44 4.1.2 Polymorphous Resources………………………………………45 4.5 Instruction, Thread and Data Level Parallelism…………46 4.5.1 Desktop Morph: Instruction Level Parallelism…………46 4.5.2 Thread Morph: Thread Level Parallelism…………………48 4.5.3 Super Morph: Data Level Parallelism……………………49 Chapter 5 Simulation 5.1 Non-reconfigurable Processors Design Simulation………52 5.1.1 One Function Unit General CPU Architecture without Reconfigurable Design.....................................52 5.1.2 Two Function Units General CPU Architecture without Reconfigurable Design.....................................55 5.1.3 Four Function Units General CPU Architecture without Reconfigurable Design....................................57 5.1.4 Nine Function Units General CPU Architecture without Reconfigurable Design………………………………………………59 5.1.5 Sixteen Function Units General CPU Architecture without Reconfigurable Design……………………………………61 5.2 Simulation with Reconfigurable Design……………………63 5.2.1 One Function Unit CPU Architecture with Reconfigurable Design………………64 5.2.2 Two Function Units CPU Architecture with Reconfigurable Design………66 5.2.3 Four Function Units CPU Architecture with Reconfigurable Design………69 5.2.4 Nine Function Units CPU Architecture with Reconfigurable Design………71 5.2.5 Sixteen Function Units CPU Architecture with Reconfigurable Design………74 5.3 Compare and Analyze Architectures………………………76 5.4 Conclusion…………………………………………………………84 Chapter 6 Reconfigurable Processor Design 6.1 Instruction Set…………………………………………………86 6.1.1 Very-Long Instruction Word…………………………………86 6.1.1.1 Architecture Comparison of CISC, RISC, and VLIW………………………86 6.1.1.2 VLIW Architectures and Implementations………………88 6.1.2 Types of Instruction Set……………………………………90 6.1.2.1 Resister Type Slot…………………………………………90 6.1.2.2 Immediate Type Slot………………………………………91 6.1.2.3 Jump Type Slot………………………………………………92 6.1.2.4 Reconfigurable Type Slot…………………………………92 6.1.2.5 Communication Type Slot…………………………………93 6.2 Hardware Architecture…………………………………………95 6.2.1 The basic principle of a CPU………………………………95 6.2.1.1 Basic Components of a CPU………………………………95 6.2.1.2 The Program Counter Datapath……………………………95 6.2.1.3 The Arithmetic Operation Datapath……………………97 6.2.2 Enhancing Performance with Pipeline……………………98 6.2.3 Sixteen Function Units Reconfigurable Processor……100 6.3 Hazards……………………………………………………………101 6.3.1 Structural hazards…………………………………………101 6.3.2 Control hazards………………………………………………101 6.3.2.1 Stall………………………………………………………101 6.3.2.2 Prediction…………………………………………………102 6.3.3 Conclusion……………………………………………………105 6.4 Reconfigurable Components Designs…………………………106 6.4.1 Reconfigurable Controller and DMA machine……………107 6.4.2 Function Unit…………………………………………………108 6.4.3 Cache……………………………………………………………109 6.4.4 Example for Reconfiguration………………………………111 6.5 Exception…………………………………………………………115 6.6 Network Interface………………………………………………116 6.7 Hierarchical Dataflow Mapping………………………………117 6.8 Conclusion………………………………………………………119 Chapter 7 Conclusion Reference………………………………………………………………123

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