在現今超大型積體電路設計中，低功率已經成為一個熱門的議題。為了處理這樣的問題，多重供應電壓源(MSV)這種設計方式已被廣泛應用於實體設計中減少動態功率消耗。為了實踐MSV，我們必須放置準位調節器(Level-Shifter)到介於兩個電壓島(Voltage Island)之間的訊號上。而準位調節器的擺置位置的結果將會對最終的平面規劃在整體平面面積與線長造成很大的影響。但到目前為止，僅有一篇論文實際考量到準位調節器的實際擺置位置。在他們的方法中，準位調節器是被放置在整個平面規劃周圍。但是為了實行準位調節器的電源規劃,我們希望將準位調節器放置到一個特定的區域稱為準位調節器管道(Level-Shifter Channel)。在這本論文中，我們提出了一種分為兩個階段的演算法來處理準位調節器擺置的問題。在分配完準位調節器管道後，我們在第一階段先使用網路流(Network Flow)演算法粗略的決定準位調節器的位置，接著第二個階段再使用整數線性規劃法(Integer Linear Programming)決定準位調節器的確切位置。實驗結果證明我們的演算法可以獲得很好的線長以及較小的面積且執行時間快速。

Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) has been widely applied to a real design to reduce dynamic-power consumption. However, to facilitate MSV, we have to insert level-shifters for those signals across different voltage islands. The placement results of level-shifters have great impact on the area and wirelength for the resulting floorplan. There exists only one work considering this issue~cite{Yu09}, and, in their methodology, level-shifters are placed around the chip. However, to facilitate power planning for level-shifters, we have better to place level-shifters in a specified region, named level-shifter channels. In this paper, we propose a two-phase algorithm to deal with the level-shifters insertion problem. After level-shifterchannels have been allocated, we first roughly determine the positions of level-shifters by applying the network flow
algorithm. Then, we use an integer linear programming (ILP) to determine the exact position of level-shifters in the second phase. The experimental results show that our algorithm can obtain better wirelength and area in a fast running time for level-shifter insertion.

[1] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, ”Introduction to Algorithm, 2nd Edition,” 2001.
[2] D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D.W. Stout, S.W. Gould, and J .M. Cohn,“Managing power and performance for system-on-chip designs using voltage islands”, In Proc. ICCAD , pp. 195-202, 2002.
[3] J.-M Lin and Y.-W Chang, “TCG: A transitive closure graph-based representation for non-slicing floorplans,” In Proc. DAC, pp. 764-769, 2001.
[4] B. Liu, Y. Cai, Q. Zhou, and X. Hong, “Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-vdd designs,” In Proc. ASP-DAC, pp. 582-587, 2006.
[5] Q. Ma and E.F.Y. Young, “Voltage island-driven floorplanning,” In Proc. ICCAD, pp. 644-648, 2007.
[6] S. G. Nash, and A. Sofer, ”Linear and Nonlinear Programming, International Editions,” 1996.
[7] D. Sengupta, R. Saleh,“Application-driven floorplan-aware voltage island design,” In Proc. DAC, pp. 155-160, 2008.
[8] John G. Spooner,“Chip designers voyage voltage island,”http://news.com.com/Chip designers voyage to voltage island/2100-1001 3-934355.html, 2002.
[9] B. Yu, S. Dong, S. Goto, and S. Chen, “Voltage-island driven floorplanning considering level-shifter positions,” in Proc. GLSVLSI, pp 51-56, 2009.