本論文提出了一種測試晶片設計，主要針對標準元件庫中組合邏輯的標準元件之小延遲缺陷進行測試及診斷。此測試晶片由定量可測試的測試陣列與掃描練所組成，並以二維形式構建以達到高可測試性及高可診斷性。本論文也提出了一種新穎的方法可將標準元件庫中的每個組合邏輯的標準元件系統性地嵌入到具有雙射性質的修改元件中，使測試陣列具定量可測試特性。為提升測試小延遲缺陷之測試解析度，我們提出了一套程序來建立測試陣列，其中包含了對修改元件進行分群與擺放的方法。分群方法會將具有相近傳送延遲時間的修改元件歸為同一群，而擺放方法則利用互相正交拉丁方陣的概念，將修改元件放置測試陣列中，使測試陣列中所有路徑的傳送延遲得以一致。實驗結果顯示，在台積電四十奈米與七奈米製程技術之下，使用雙向連接測試陣列之測試晶片的測試解析度分別可達到0.061奈秒及0.032奈秒，而使用三向連接測試陣列之測試晶片則可達到0.086奈秒及0.051奈秒，而類似的方法也可應用於更先進的製程技術中。

In this thesis, we propose a test chip design that aims to test and diagnose the small delay faults of combinational cells in a cell library. The test chip is composed of C-testable test arrays and scan registers that are constructed in a two-dimensional format so as to achieve high testability and diagnosability. We present a novel approach to systematically map each standard cell to a modified cell with the bijection property to make the test arrays C-testable. To enhance the test resolution for the small delay defects (SDDs) testing, we propose a procedure consisting of a grouping method and a placement method. The grouping method classifies the modified cells with similar delay values into the same group. The placement method leverages the concept of mutually orthogonal Latin squares to place the modified cells in the test arrays such that the delays on the I-O paths in the test chip are balanced. Experimental results show that under TSMC 40nm and 7nm process technologies, the test resolution of the test chips using bidirectionally connected test arrays can achieve 0.061 ns and 0.032 ns, respectively, while the test chips using tridirectionally connected test arrays can achieve 0.086 ns and 0.051 ns. Similar approach can be applied to more advanced process technology.

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