| 研究生: |
朱彥嘉 Chu, Yen-Chia |
|---|---|
| 論文名稱: |
於低功率應用之可編程邏輯閘陣列開發可程式化直流對直流電壓調節器 Implementation of the Programmable DC-DC Voltage Regulator by FPGA for Low Power Applications |
| 指導教授: |
張簡樂仁
Chang-Chien, Le-Ren |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2008 |
| 畢業學年度: | 96 |
| 語文別: | 中文 |
| 論文頁數: | 89 |
| 中文關鍵詞: | 參考電壓 、直流對直流降壓式動態電壓調節器 、可編程邏輯閘陣列板 、數位補償器 |
| 外文關鍵詞: | dynamic voltage scaled DC-DC step-down voltage r, voltage references, digital compensator, Field Programmable Gate Array |
| 相關次數: | 點閱:84 下載:3 |
| 分享至: |
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本論文為積體電路架構下,提出一可程式化數位控制直流對直流降壓式動態電壓調節器。本提出的電壓調節器不需要由band-gap產生不同的參考電壓,來滿足不同電路對不同電壓等級的需求。因此可以簡單的以數位碼控制調節器的輸出電壓,而不用擔心CMOS堆疊限制以及製程飄移的影響。本電壓調節器控制單元由浮點數數位補償器在可編程邏輯閘陣列板上(Field Programmable Gate Array, FPGA)驗證,並於驗證之後向國家實驗研究院晶片系統設計中心(CIC)提出了下線計畫。FPGA的驗證結果展示,在5伏特到8伏特的輸入電壓範圍之下,都可使電壓調節器穩定的輸出1.8伏特、2.7伏特及3.3伏特3種等級的電壓,並且供應的負載電流可達到2.5安培以上。
This thesis proposes a programmable dynamic voltage scaled DC-DC step-down voltage regulator for integrated circuits (ICs). The proposed voltage regulator does not need the band-gap voltage references to generate various desired voltages for circuit loads. Therefore, the output voltage of the converter could be assigned by any voltage level for ICs without considering the effects of the CMOS stack limit and IC processing drift. The control unit of the proposed converter is realized by a floating-point digital compensator on a Field Programmable Gate Array (FPGA). After that, we apply the chip fabrication to CIC (National Chip Implementation Center). Lab experiments show that the proposed converter can supply stable voltage levels at 1.8V, 2.7V and 3.3V with variant input voltage ranging from 5V-8V. The load current could be supplied up to 2.5A.
[1] M. Hiraki, T. Ito, A. Fujiwara, T. Ohashi, T. Hamano, and T. Noda, “A 63-μW Standby Power Microcontroller With On-Chip Hybrid Regulator Scheme,” IEEE J. of Solid-State Circuits, vol. 37, no. 5, pp. 605-611, May. 2002.
[2] A. Cabrini, G. De Sandre, L. Gobbi, P. Malcovati, M. Pasotti, M. Poles, F. Rigoni and G. Torelli, “A 1V, 26μW Extended Temperature Range Band-gap Reference in 130-nm CMOS Technology,” IEEE ESSCIRC 2005, pp. 503-506.
[3] Gene F. Franklin, J. David Powell, Michael L. Workman, “Digital Control of Dynamic Systems 2nd Edition,” Addison-Wesley Publishing Company, pp.223-224.
[4] B. J. Patella, A. Prodic´, A. Zirger, and D. Maksimovic´, “High-Frequency Digital PWM Controller IC for DC-DC Converters,” IEEE Tran. on Power Electronics, vol. 18, issue 1, part 2, pp. 438-446, January 2003.
[5] Y. Ishizukat, M. Uenott, I. Nishikawat, A. Ichinoset and H. Matsuot,” A Low-Delay Digital PWM Control Circuit for DC-DC Converters,” IEEE APEC 2007, pp. 579-584.
[6] 游宗穎, “具有脈衝寬度調變和脈衝頻率調變之同步高效互補式金氧半切換示穩壓器,” 國立交通大學電子工程學系電子研究所碩士論文, 2003.
[7] K. Leung, D. Alfano, “Design and Implementation of a Practical Digital PWM Controller,” IEEE APEC 2006, pp. 1437-1442.
[8] R. E. Foley, R. C. Kavanagh, W. P. Mamane, and M. G. Egan, “An Area-Efficient Digital Pulsewidth Modulation Architecture Suitable for FPGA Implementation,” IEEE APEC 2005, pp. 1412- 1418.
[9] Z. Lukic´, N. Rahman, and A. Prodic´, “Multibit Sigma-Delta PWM Digital Controller IC for DC-DC Converters Operating at Switching Frequencies Beyond 10 MHz,” IEEE Trans. on Power Electronics, vol. 22, no. 5, pp. 1693-1707, Sep. 2007.
[10] A. V. Peterchev, and S. R. Sanders, “Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters,” IEEE Trans. on Power Electronics, vol. 18, no.1, pp. 301-308, Jan. 2003.
[11] S. Chattopadhyay and S. Das, “A Digital Current-Mode Control Technique for DC–DC Converters,” IEEE Trans. on Power Electronics, vol. 21, no. 6, pp.1718-1726, Nov. 2006
[12] A. V. Peterchev, Jinwen Xiao, and S. R. Sanders, “Architecture and IC Implementation of a Digital VRM Controller,” IEEE Trans. on Power Electronics, vol. 18, no.1, pp. 356-364, Jan. 2003.
[13] Yang Qiu, Jian Li, Ming Xu, Dong S. Ha, Fred C. Lee, “Proposed DPWM Scheme with Improved Resolution for Switching Power Converters,” IEEE APEC 2007, pp. 1588-1593.
[14] S. C. Huerta', A. d. Castro, 0. Garcia', J.A. Cobos', “FPGA Based Digital Pulse Width Modulator with Time Resolution under 2 ns,” IEEE APEC 2007, pp. 877-881.
[15] Jian Li, Yang Qiu, Yi Sun, Bin Huang, Ming Xu, Dong S. Ha, Fred C. Lee, “High Resolution Digital Duty Cycle Modulation Schemes for Voltage Regulators,” IEEE APEC 2007, pp. 871-876.
[16] H. Peng, D. Maksimovic, A. Prodic, E. Alarco’n, “Modeling of Quantization Effects in Digitally Controlled DC-DC Converters,” IEEE PESC 2004, pp. 4312-4318.
[17] A. Prodic and D. Maksimovic, “Digital PWM Controller and Current Estimator for A Low-Power Switching Converter,” IEEE COMPEL 2000, pp. 123-128.
[18] L. Richard Carley, and Akshay Aggarwal, “A Completely On-Chip Voltage Regulation Technique For Low Power Digital Circuits,” IEEE Low Power Electronics and Design 1999, pp.109 – 111.
[19] Vorperian V. ”Simplified Analysis of PWM Converters Using Model of PWM Switch. Continuous Conduction Mode,” IEEE Trans. Aerospace and Electronic Systems, vol. 26, Issue 3, pp.490 - 496, May 1990
[20] Vorperian V., “Simplified Analysis of PWM Converters Using Model of PWM Switch. II. Discontinuous Conduction Mode,” IEEE Trans. on Aerospace and Electronic Systems, vol. 26, Issue 3, pp.497 – 505, May 1990
[21] Ka Nang Leung, and Philip K. T. Mok, “A Capacitor-Free CMOS Low-Dropout Regulator With Damping-Factor-Control Frequency Compensation,” IEEE J. of Solid-State Circuits, vol. 38, no. 10, October 2003
[22] Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin’ichiro Kimura, Narumi Sakashita, Tadashi Tachibana, Katsutaka Kimura, “A Precise On-Chip Voltage Generator for a Gigascale DRAM with a Negative Word-Line Scheme,” IEEE J. of Solid-State Circuits, vol. 34, no. 8, August 1999
[23] C. H. Wu, Le-Ren Chang-Chien, Lih-Yih Chiou “Active Filter Based On-Chip Step-Down DC-DC Switching Voltage Regulator,” IEEE TENCON 2005, pp.1-6
[24] Wu A.M., Jinwen Xiao, Markovic D., Sanders S.R. “Digital PWM Control: Application in Voltage Regulation Modules”, IEEE Power Electronics Spec. Conf. 1999, vol.1, pp.77-83
[25] Arabi K., Kaminska B., “Oscillation-Test Strategy for Analog and Mixed-Signal Integrated Circuits,” IEEE VLSI Test Symposium 1996, pp.476 – 482
[26] Ohltz, M.J, “Hybrid Built-In Self Test Structure for Mixed Analog/Digital Integrated Circuits,” IEEE 2nd European Test Conference 1991, pp. 307-316
[27] Arabi K., Kaminska B. “Testing Analog and Mixed-Signal Integrated Circuits Using Oscillation-Test Method” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, Issue 7, pp.745 – 753, July 1997
[28] J. Xiao, A. V. Peterchev, J. Zhang, S.R. Sanders, “A 4μA-Quiescent-Current Dual-Mode Buck Converter IC for Cellular Phone Applications,” IEEE J. on Solid State Circuits, vol. 39, Issue 12, pp. 2342-2348, Dec. 2004.
[29] George Patounakis, Yee William Li, Kenneth L. Shepard, “A Fully Integrated On-Chip DC-DC Conversion and Power Management System,” IEEE J. of Solid-State Circuits, vol. 39, no. 3, pp.433-451, March 2004.
[30] Clare G. Keeney, and Malcolm Mcwhorter, “A Highly Efficient Inductorless Voltage Regulator,” IEEE J. of Solid-State Circuits, vol. sc-4, no. 4, pp.192-198, August 1969.
[31] 黃子龍, “精確的2.5伏特轉為1.8伏特的低壓降穩壓器”, 國立成功大學電機工程學系碩士論文, 2003.
[32] Stratakos A.J., Sanders S.R., Brodersen R.W., “A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System,” IEEE PESC. 1994, vol.1, pp.619 – 626.
[33] Arbetter B., Erickson R., Maksimovic D. “DC-DC Converter Design for Battery-Operated Systems,” IEEE PESC. 1995, vol.1, pp.103 – 109.
[34] Wai Lau, Sanders S.R., “An Integrated Controller for a High Frequency Buck Converter,” IEEE PESC. 1997, vol.1, pp.246 – 254.
[35] Kursun V., Narendra S.G., De V.K., Friedman E.G. “Monolithic DC-DC Converter Analysis and MOSFET Gate Voltage Optimization,” IEEE Quality Electronic Design 2003 , pp.279 – 284.
[36] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Analysis of Buck Converters for On-Chip Integration with a Dual Supply Voltage Microprocessor,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp.514-522, June 2003.
[37] V. Kursun, V. K. De, E. G. Friedman, and S. G. Narendra, “Monolithic Voltage Conversion in Low Voltage CMOS Technologies,” Microelectronics Journal ISSN, Vol. 36, Issue 9, pp. 863-867, September 2005
[38] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, “Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages,” International Journal of Analog Integrated Circuits and Signal Processing, vol. 42, no. 3, pp.231-238, March 2005.
[39] D. Maksimovic, R. Zane, R. Erickson, “Impact of Digital Control in Power Electronics,” IEEE Power Semiconductor Devices & ICs 2004, pp.13-22.
[40] B. Miao, R. Zane, D. Maksimovic, “System Identification of Power Converters with Digital Control through Cross-Correlation Methods,” IEEE Trans. on Power Electronics, vol. 20, no. 5, pp.1093-1099, Sept. 2005.
[41] Mike Wai-Tak Wong, “On the issues of oscillation test methodology,” IEEE Trans. on Instrumentation and Measurement, vol. 49, Issue 2, pp.240-245, April 2000.
[42] Arabi, K.; Kaminska, B., “Oscillation-Test Methodology for Low-Cost Testing of Active Analog Filters,“IEEE Trans. on Instrumentation and Measurement, vol. 48, Issue 4, pp.798-806, Aug. 1999
[43] Zarnik M.S., Novak F., Macek S., “Design of Oscillation-Based Test Structures for Active RC Filters,” IEE Circuits, Devices and Systems, vol. 147, Issue 5, pp.297-302, Oct. 2000
[44] Sahu B., Rincon-Mora G. A. “An Accurate, Low Voltage, CMOS Switching Power Supply with Adaptive On-Time Pulse-Frequency Modulation (PFM) Control,” IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 54, Issue 2, pp.312-321, Feb. 2007.
[45] Siyuan Zhou, Rincon-Mora G.A., “A High Efficiency, Soft Switching DC-DC Converter with Adaptive Current-Ripple Control for Portable Applications,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 53, Issue 4, pp.319-323, April 2006.
[46] Burns, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press 2001
[47] Mark Baker, “Demystifying Mixed Signal Test Methods,” Newnes, 2003.