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研究生：	羅偉綸 Lo, Wei-Lun
論文名稱：	以比較器為基礎架構之三角調變積分器設計 Design of Comparator-Based Switched-Capacitor Sigma-Delta Modulator
指導教授：	劉濱達 Liu, Bin-Da
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	62
中文關鍵詞：	三角調變積分器、以比較器為基礎架構的切換電容式電路
外文關鍵詞：	Sigma-delta modulator, comparator-based switched-capacitor circuit
相關次數：	點閱：73 下載：0
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近來廣泛應用以比較器為基礎架構的切換電容式電路，主要是將傳統電路中的運算放大器以比較器及電流源來取代，藉此達到低功率消耗與降低面積的優點。然而，因為過充電壓會影響其準確性，而且兩段式充放電限制了取樣速度，所以這篇論文提出新的充電方式，以解決過充問題及提高取樣速度，其方法是取樣過充電壓，使輸入比較器的參考電壓改變進而得到準確的輸出值。此架構只需要一段式充電，所以取樣速度可以大幅提升。
本論文使用0.18 μm一層多晶矽六層金屬之互補式金氧半製程，實現一個供應電壓為1.8 V，取樣頻率為50 MHz之二階三角積分調變器。當此三角調變積分器的超取樣比為32時，在781.25 kHz的信號頻寬內可達到52 dB的訊號對雜訊加失真比(SNDR)，整個電路的功率消耗為3.85 mW。

A comparator-based switched-capacitor (CBSC) circuit topology is introduced comprehensively, it replaces the operational amplifier by a threshold-detection comparator and current sources, then the power consumption and active area can be decreased. However, the overshoot voltage affects the resolution and the two charge transfer phases limit the sampling frequency. This thesis propose a new method of charge transferring to solve the overshoot problem and increase the sampling speed. To obtain the precise output value, the proposed architecture adjusts the reference voltage of comparator by sampling the overshoot voltage. Moreover, there is only one current source of this structure, the sampling frequency is increased.
This second-order ΣΔ ADC with a 1.8-V supply voltage has been designed in 0.18-μm CMOS process without low threshold MOS devices. The modulator achieves 52-dB SNDR within the signal bandwidth of 781.25 kHz, the sampling frequency is 50 MHz, which corresponds to an oversampling ratio of 32, the total power consumption is 3.85 mW.

Abstract i
Acknowledgement iii
Table of Content v
List of Figures xiii
List of Tables xi
Chapter 1 Introduction	1
1 Motivation	1
2 Thesis Organization	2
Chapter 2 Fundamentals of Delta-Sigma Converter	4
1 Introduction of ADCs	5
2 Sigma-Delta Modulators	7
2.1 Quantization error	7
2.2 Oversampling technique	11
2.3 Noise shaping technique	13
3 Sigma-Delta Modulators Topologies	15
3.1 First-order sigma-delta modulator	15
3.2 Second-order sigma-delta modulator	16
3.3 High order sigma-delta modulator	18
3.4 MASH (Multi-Stage Noise Shaping) sigma-delta modulator	19
4 Summary	21
Chapter 3 Comparator-Based Switched-Capacitor (CBSC) Circuits	22
1 Practical Charge Transfer Phase in CBSC Circuits	22
2 Proposed CBSC Circuits	25
2.1 CBSC gain stage	25
2.2 Odd phase of CBSC gain stage	27
2.3 Even phase of CBSC gain stage	29
3 Summary	30
Chapter 4 CBSC 2nd-Order SDM with Overshoot Reduction	31
1 Circuit Non-ideality	31
1.1 Thermal noise	32
1.2 Charge injection errors	33
1.3 Clock feedthrough	34
2 System Architecture	35
2.1 Input feed-forward structure	35
2.2 Second-order input feed-forward sigma-delta modulator	37
3 Circuit Architecture	39
3.1 Single-ended second-order sigma-delta modulator	39
3.2 Threshold-detection comparator	44
3.3 Ramp generator	47
3.4 1-bit quantizer	47
3.5 Clock generator	48
4 Simulation Results and Comparison	52
4.1 MATLAB model simulation	52
4.2 Pre-layout simulation results	52
4.3 Layout consideration	55
4.4 Performance comparison	57
Chapter 5 Conclusions and Future Work	58
1 Conclusions	58
2 Future Work	59
References	60

                                    

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校內：2012-08-02公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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