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研究生：	劉健德 Liu, Chien-Te
論文名稱：	CASL Hypervisor與其虛擬化平台 CASL Hypervisor and its Virtualization Platform
指導教授：	陳中和 Chen, Chung-Ho
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	79
中文關鍵詞：	電子系統層級設計、虛擬化、全系統模擬
外文關鍵詞：	electronic system level, virtualization, full system simulation, hypervisor
相關次數：	點閱：100 下載：1
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近年來隨著硬體架構的支援，虛擬化可以在不修改客戶端作業系統的情況下進行實作。這篇論文提出一個基於 ARM架構的 CASL Hypervisor 以及一個全系統虛擬化平臺，使得早期的軟硬體協同模擬及開發更加方便而有效率。
利用了新增加的處理器模式、兩階段的記憶體管理以及客製化的硬體，CASL Hypervisor 可以在不更改客戶端作業系統的情況下進行虛擬化。由於硬體上的支援，CASL Hypervisor 的開發時間大幅縮短，並且具有更加快速的效能；全系統模擬平台上的 GDB 及相關記錄工具更加簡化了除錯上的難度。
模擬數據是利用approximagely-timed的全系統模擬平臺進行。數據顯示 CASL Hypervisor 可以同時支援四個客戶端作業系統同時維持極佳的效能。

With the introduction of hardware extensions to recent ARM processors, virtualization can be done in a more flexible manner with no need to modify guest kernel. This thesis proposes the ARM-based hardware-assisted CASL Hypervisor and a full system virtualization platform which enables software/hardware co-simulation of virtual machine monitor at the early development stage.
CASL Hypervisor takes advantage of an additional processor mode, extended memory management unit, configurable hardware traps and specialized hardware devices to virtualize unmodified Linux-based guest operating systems. By utilizing hardware extensions, development effort of CASL Hypervisor can be greatly reduced and maintain relatively low virtualization overhead at the same time. Since the full system simulation platform is based on SystemC, hardware simulation models can not only be built fast but also conveniently modified to evaluate different implementations. With the simulation platform's built-in GDB stub and log facility, the complexity of debugging software/hardware interactions can be greatly reduced.
Evaluation is demonstrated on an approximately-timed manner so it is able to do fast software/hardware co-simulation and evaluations. The results show that CASL Hypervisor can successfully virtualize four guest operating systems with little overhead.

Introduction 1
Background 3
1 Virtualization Overview 3
1.1 Binary Translation 3
1.1.1 Interpretive Translation 3
1.1.2 Static Compiled Translation 4
1.1.3 Dynamic Compiled Translation 4
1.2 Paravirtualization 5
1.3 Full Virtualization 5
2 Full System Simulation 5
Related Work 7
1 Xen 7
2 Xen on ARM 8
3 Kernel-based Virtual Machine 8
4 KVM for ARM 9
5 Full Virtualization with TrustZone 10
6 OKL4 Microvisor 11
Full System Virtualization Platform Architecture 13
1 The Accuracy Model of Simulation 14
2 ARMv7 Instruction Set Simulator 14
2.1 Data-path 15
2.2 Privilege Levels and Processor Modes 15
2.3 Coprocessors 17
2.4 Exceptions 18
2.5 Wait for Interrupt Instruction 19
2.6 Hypervisor Trap 19
2.7 The Security Extensions 20
3 Virtual Memory System Architecture 21
3.1 Short-Descriptor Translation Table Format 22
3.2 Long-Descriptor Translation Table Format 22
3.3 Two Stage Virtual Address Translation 23
4 Transaction-Level Modelling Bus 24
5 Device Modules 25
5.1 Generic Interrupt Controller 25
5.2 Timer 27
5.3 Universal Asynchronous Receiver/Transmitter 28
5.4 Semi-host Device 28
CASL Hypervisor Architecture 29
1 Guest Operation System 30
2 C Environment 31
2.1 Stack 31
2.2 The C Standard Library 31
2.3 Semi-host 32
3 Booting Guest Operating System 33
4 CPU Virtualization 33
4.1 Control Transfer 33
4.2 Hypervisor Traps 35
5 Memory Virtualization 36
5.1 Page Tables 36
5.2 Stage One Page Table 38
5.3 Stage Two Page Table 39
5.4 On-demand Memory Allocation 40
6 Device Virtualization 41
6.1 Implementing Virtual and Pass-through Devices 41
6.2 System Controller 42
6.3 Generic Interrupt Controller 43
6.4 Timer 44
6.5 UART 44
7 Interrupt Virtualization 45
7.1 Interrupt Handling in Non-Virtualized Environment 45
7.2 Interrupt Handling in Virtualized Environment 46
7.3 Interrupts Service Routines 47
8 Virtual Machine Scheduling 48
8.1 Virtual Machine Context 48
8.2 Scheduler 49
8.2.1 Scheduling Method 49
9 Comparison with Other Works 50
10 Memory Map 51
10.1 Main Memory 51
10.2 General Devices 51
10.3 Pass-through Devices 52
11 CASL Hypervisor High-level Program Architecture 52
11.1 Initialization Process of CASL Hypervisor 52
11.2 Entry Points to CASL Hypervisor 53
Experimental Results 55
1 Complexity 55
2 Host Configuration 55
3 Virtualization Platform Configuration 56
4 LMBench 57
4.1 Basic System Operations 57
4.2 Latency and Overhead 58
5 SPEC CPU2000 64
6 Processor Utilization Rate 65
7 A FIFO-based Simulation Approach for Real-time Applications 69
7.1 Evaluation of Real-time MPEG Layer-3 Audio Decoding 70
Conclusion and Future Work 75
Bibliography 77
                                    

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