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研究生：	王子綸 Wang, Zi-Lun
論文名稱：	應用於網路路由器之低功率特定指令集處理器設計 Design of a Low Power ASIP for Network-on-Chip Routing
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	83
中文關鍵詞：	路由器、低功率、處理器
外文關鍵詞：	low power, processor, router
相關次數：	點閱：80 下載：1
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特定應用處理器(ASIP)和網路晶片的設計方法在系統晶片設計和學術研究單位裡已經獲得廣大歡迎。然而網路晶片應用對ASIP的記憶體存取功率損耗卻佔了系統功率的一大部分(%20~%40)或更多。在本論文裡我們已經設計了一個應用於網路晶片路由器之低功率ASIP來解決此問題。因為指令封裝可以有效的減少功率損耗，所以我們的ASIP採用VLIW指令架構藉由增加指令平行度來減少記憶體存取進而降低記憶體的功率的損耗。為了達到更好且平衡的設計我們使用EXPRESSION作為設計探索的工具。因為此NoC路由器是一個蟲洞-虛擬通道架構，所以會有大量的虛擬通道位置要計算，根據此特性，我們發展新的指令集可以減少記憶體的存取次數進而降低記憶體存取的功率損耗。更進一步我們利用Verilog和合成的軟體實現了此ASIP且進行了許多實驗。藉由最後的實驗結果可以看出有效的效能提升和記憶體功率損耗的下降

Application-Specific Instruction-set Processors (ASIPs) and Network-on-a-Chip (NoC) design approaches have gained popularity in SoC designs as well as in the research community. However, the power dissipation of ASIP memory access for a NoC application often occupies a great deal of system power (25%~40%) or more. In this thesis, we have designed a low power ASIP for the NoC router applications to solve the issue. Since the instruction packing can efficiently decrease the power dissipation, so our low power ASIP design adopts the VLIW architecture by increasing its instruction parallelism, decreasing the number of memory access to reduce memory power consumption. In order to get a good and balanced ASIP design, we used the EXPRESSION as an ASIP architectural exploration tool. Since the NoC router is a wormhole-virtual channel structure and a mass position of virtual channels must to be computed, we developed a new instruction set for the router to decrease its memory access and then to reduce its memory access power. Moreover, we implemented the ASIP in Verilog with synthesis tools and did many experiments for it. Effective increasing in the performance and decreasing in the power dissipation of the ASIP are observed from the final experimental results.

Abstract.......................................................................V

Chapter 1 Introduction.........................................................1

Chapter 2 The low power ASIP design for NoC routing............................4
    2.1 Introduction...........................................................4
    2.2 Behavior model for NoC routers.........................................5
        2.2.1 Behavior model for receive.......................................6
        2.2.2 Behavior model for idle..........................................6
        2.2.3 Behavior model for routing.......................................7
        2.2.4 Behavior model for virtual-channel-allocation-request............7
        2.2.5 Behavior model for virtual-channel-allocation-grant..............8
        2.2.6 Behavior model for virtual-channel-allocation-accept.............9
        2.2.7 Behavior model for switch-allocation-request.....................9
        2.2.8 Behavior model for switch-allocation-grant......................10
        2.2.9 Behavior model for switch-allocation-accept.....................11
        2.2.10 Behavior model for crossbar traverse...........................11
    2.3 Router application analysis...........................................12
    2.4 The routing ASIP design based on EXPRESSION...........................14
    2.5 Exploration for routing ASIP..........................................15
    2.6 Design space exploration for low power................................17
    2.6.1 Loop combination....................................................18
    2.6.2 Instruction ordering................................................21
    2.6.3 Hybrid methods for minimizing power.................................21

Chapter 3 Introduction for EXPRESSION.........................................22
    3.1 Simulator/compiler toolkit............................................23
    3.2 EXPRESSION organization...............................................25
    3.3 Operation specification...............................................25
    3.4 Instruction...........................................................26
    3.5 Operation mappings....................................................28
    3.6 Components specification..............................................30
    3.7 Pipeline and data transfer paths......................................31
    3.8 Memory subsystem......................................................32
    3.9 Power model of the memory system......................................34

Chapter 4 Architecture Implementation.........................................35
    4.1 Routing ASIP Architecture.............................................35
    4.2 Instruction format for slot...........................................36
    4.3 Handling control signal...............................................37
    4.4 Register file overview................................................38
    4.5 Hazard solution.......................................................39
        4.5.1 Data dependency.................................................39
        4.5.2 Solution of control hazard......................................42

Chapter 5 Experiment Results..................................................44
    5.1 Results of original architecture......................................44
    5.2 Results of adding new (complex) istructions...........................47
    5.3 Results of loop combination...........................................49
    5.4 Results of instruction ordering.......................................52
    5.5 Results of loop combination + instruction ordering....................54
    5.6 Results of adding new (complex) instruction + instruction ordering....57
    5.7 Results of adding complex instruction + loop combination..............59
    5.8 Results of adding new instruction + loop combination + instruction  
        ordering..............................................................62
    5.9 Experiment result analysis............................................64
    5.10 Results of code size.................................................67
    5.11 Results of synthesis.................................................68

Chapter 6 Conclusion and future work..........................................69

References....................................................................70

Appendix A: Architecture Description Language of the NoC Router ASIP..........72

Appendix B: The instructions for NoC routing ASIP.............................82


                                    

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校內：2006-07-28公開
校外：2006-07-28公開

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