此論文提出的動態估計系統架構為基於演算法暨架構共同探索設計方法所設計，使用由粗顆粒動態向量淬鍊至細顆粒的方法保有極佳演算法效能，於設計演算法時便同時考量架構資訊，而非只專注於改善其精確度的演算法效能之動態估計演算法，卻忽略了伴隨著極高頻寬與繁複運算造成不實際的架構實現，於初期設計運用不同的資料流萃取相對應的本質演算法複雜度以取得系統架構的特性，並評估是否返回修改高抽象層級設計來減少設計成本，於目標規格下，所提出之系統架構已成功實現並驗證於現場可程式化閘陣列平台，支援1920×1080解析度可由60禎率提升至120禎率，時脈操作於148.5赫茲。

The present thesis proposes the system architecture of motion estimation (ME) based on an algorithm/architecture co-exploration (AAC) design methodology, which is proven to have excellent algorithm performance, with the refinement of the coarse-grained motion vector (MV) into a fine-grained MV. Architecture information is considered in designing the algorithm. However, the use of complex algorithms to enhance the accuracy of ME in terms of algorithm performance is not considered because of the extremely high bandwidth and unduly complex computation required, consequently making their implementation impractical. Varying dataflow enables extraction across a range of intrinsic algorithm complexities as a means to characterize the significance of information related to system architecture in the early phases of design. The intrinsic complexity of the algorithm must be appraised to determine whether back-annotation to a higher level of abstraction should be applied to reduce design costs. In accordance with the target specifications, the proposed system architecture was successfully implemented and verified on a field-programmable array gate (FPGA) board for motion-compensated frame rate up-conversion (MC-FRUC), supporting frame rates from 60 up to 120 frames per second (fps) with a 1920×1080 resolution and at a clock rate of 148.5 MHz.

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