硬體層的行為對大部分的程式設計師而言就像是個黑箱，這將導致電路設計在開發或除錯上的困難，因此本篇論文提供一套基於FPGA的平台讓設計師在CPU執行期間能即時看到底層的硬體行為或訊號。
在本篇論文中，該平台分成軟體與硬體兩部分。在軟體部分我們定義若干APIs來管理硬體層的核心並即時接收硬體層的訊號；而硬體部分是在FPGA開發板上建構一套基於OpenRISC架構的多核心系統，並以mailbox的方式實現多核心間的資料傳輸。兩者透過USB介面做相連並根據我們定義的協定(Baton protocol)做資料交換。
雖然目前是以OpenRISC做CPU架構，但只要遵守我們定義的Baton protocol與Baton APIs，不管是CPU、記憶體，或是周邊設備都可以做替換。我們所提出的FPGA平台與工具提供了開發者在設計電路時的可變性與方便性。

For most programmers, the behavior of hardware level is like a black-box. It usually brings difficulties in developing and debugging circuit designs. Therefore, this work proposes a FPGA-based platform for observing the signal or behavior of hardware while execution.

In this thesis, the proposed platform is divided into 2 parts, hardware and software parts. In the software part, we defined several APIs to manage many cores on hardware level and observe the signals while execution in real-time. In the hardware part, on FPGA development board, we built a many-core system based on OpenRISC and used the mailbox method for communication among cores. The data transmission between hardware and software is through an USB interface which is requested to follow our defined protocol called Baton protocol.

Although we temporarily used OpenRISC as CPU in our current platform, the components of software and hardware parts (e.g. CPU, memory and peripherals) could be replaced in demand as long as they followed our defined Baton protocol and Baton APIs. The proposed platform and tools provide the flexibility and convenience for programmers in developing their circuit designs.

[1] OpenCores, http://opencores.org/
[2] Ching-Hsiang Chuang, System level Software Simulation for Hardware Implementation and its Incremental Verification with Application to H.264 Main Profile Decoder, master thesis, NCKU, 2007
[3] Yi-Li Lin, Versatile PC/FPGA Based Verification/Fast Prototyping Platform with Application to H.264/AVC 1-Frame Encoder, master thesis, NCKU, 2004
[4] Chun-Wei Lin, Baton Control Unit IP core specification
[5] Chun-Wei Lin, DDR3_BUS IP core specification
[6] Chun-Wei Lin, DDR3_Interface IP core specification
[7] OR1200 Rev 1, http://opencores.org/openrisc,file,b3IxMjAwLXJlbDEudGFyLmJ6Mg
[8] Chun-Wei Lin, External Interrupt Generator IP core specification
[9] Wishbone Bus Rev 2, http://opencores.org/download,wb_conmax
[10] OpenCores, UART 16550 IP core specification
[11] Chun-Wei Lin, ram_top IP core specification