| 研究生: |
周子翔 Chou, Tzu-Hsiang |
|---|---|
| 論文名稱: |
一實現於FPGA的乙太網音訊/視訊處理系統 An Audio/Video Processing System with Gigabit Ethernet: An FPGA Implementation |
| 指導教授: |
陳進興
Chen, Chin-Hsing |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 68 |
| 中文關鍵詞: | 現場可程式化邏輯閘陣列(FPGA) 、乙太網路 、音訊處理 、視訊處理 、影片串流 、數位訊號處理 、空間音頻 |
| 外文關鍵詞: | Ethernet, Audio Processing, Video Processing, Video Streaming, Digital Signal Processing, Spatial Audio |
| 相關次數: | 點閱:373 下載:0 |
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本論文以FPGA實現一個具有超高速乙太網路架構的多媒體處理系統。此系統能將電腦或是電視的音訊/視訊,透過乙太網路傳輸到具有IP位址的端點。由於具有音訊/視訊處理能力,我們的系統可以形成一個高速、易用但是卻強大的多媒體串流系統。
目前已實作的硬體包括兩個部分,第一部分是通過超高速乙太網路實現音訊/視訊傳輸,只要設備能接入乙太網路,就可以將數據從主機發送到設備上,實現串流媒體效果。第二部分是音訊處理,以特定的演算法對聲音進行增強,擴大聲場與濾波,利用聽覺對空間和頻率的感受性,模擬出影院級的聲音空間感和低音效果。實驗結果顯示我們已實現的系統可以經由區域網路或廣域網路將音訊/視訊傳輸到具有IP位置的任意裝置上,而經過接收端處理後的音訊具有明顯的聲場效應與頻段強化效果。
This thesis deals with FPGA implementation of an audio/video processing system with a Gigabit Ethernet architecture. Using this system, we can transfer audio/video from point to point on the ethernet. Our system equipped with signal processing capabilities, forms a high-speed, easy-to-use, yet powerful multimedia streaming system.
The implementation of our system consists of two parts. The first part realizes the data transmission of audio/video through the Gigabit Ethernet network. As long as a device can access the ethernet network, we can send the data from the host to the device and achieve the streaming media effect. The second part realizes the processing of audio signals. In this module sound are processed by specific algorithms to produce aural spatial effect and frequency enhancement. The experimental results shows that our system can stream audio/video signals from one PC to another via LAN and WLAN successfully. The audio processed at the receiving end show significant sound effect and frequency enhancement.
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