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研究生: 周子翔
Chou, Tzu-Hsiang
論文名稱: 一實現於FPGA的乙太網音訊/視訊處理系統
An Audio/Video Processing System with Gigabit Ethernet: An FPGA Implementation
指導教授: 陳進興
Chen, Chin-Hsing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 68
中文關鍵詞: 現場可程式化邏輯閘陣列(FPGA)乙太網路音訊處理視訊處理影片串流數位訊號處理空間音頻
外文關鍵詞: Ethernet, Audio Processing, Video Processing, Video Streaming, Digital Signal Processing, Spatial Audio
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  • 本論文以FPGA實現一個具有超高速乙太網路架構的多媒體處理系統。此系統能將電腦或是電視的音訊/視訊,透過乙太網路傳輸到具有IP位址的端點。由於具有音訊/視訊處理能力,我們的系統可以形成一個高速、易用但是卻強大的多媒體串流系統。
    目前已實作的硬體包括兩個部分,第一部分是通過超高速乙太網路實現音訊/視訊傳輸,只要設備能接入乙太網路,就可以將數據從主機發送到設備上,實現串流媒體效果。第二部分是音訊處理,以特定的演算法對聲音進行增強,擴大聲場與濾波,利用聽覺對空間和頻率的感受性,模擬出影院級的聲音空間感和低音效果。實驗結果顯示我們已實現的系統可以經由區域網路或廣域網路將音訊/視訊傳輸到具有IP位置的任意裝置上,而經過接收端處理後的音訊具有明顯的聲場效應與頻段強化效果。

    This thesis deals with FPGA implementation of an audio/video processing system with a Gigabit Ethernet architecture. Using this system, we can transfer audio/video from point to point on the ethernet. Our system equipped with signal processing capabilities, forms a high-speed, easy-to-use, yet powerful multimedia streaming system.
    The implementation of our system consists of two parts. The first part realizes the data transmission of audio/video through the Gigabit Ethernet network. As long as a device can access the ethernet network, we can send the data from the host to the device and achieve the streaming media effect. The second part realizes the processing of audio signals. In this module sound are processed by specific algorithms to produce aural spatial effect and frequency enhancement. The experimental results shows that our system can stream audio/video signals from one PC to another via LAN and WLAN successfully. The audio processed at the receiving end show significant sound effect and frequency enhancement.

    摘 要 I Abstract II 誌 謝 IV Acknowledgment V Contents VI List of Tables IX List of Figures X Chapter 1 Introduction 1 1.1 Field Programmable Gate Array (FPGA) 1 1.2 Gigabit Ethernet 2 1.3 Digital Audio 3 1.4 Motivation and Contribution 3 1.5 Thesis Outline 4 Chapter 2 Archeture of the proposed system and its related background knowledge 5 2.1 Hardware Architecture of the Proposed System 5 2.1.1 Programming Interface 6 2.1.2 Cyclone IV E FPGA 7 2.1.3 Marvell 88E1111 Gigabit Ethernet Transceiver 7 2.1.4 Wolfson WM8731 Audio Codec 8 2.2 Physical Layer Specification 8 2.2.1 Open Systems Interconnection (OSI) Model 8 2.2.2 Physical Layer 9 2.2.3 Reduced Gigabit Media Independent Interface (RGMII) 11 2.3 Network Packet 13 2.3.1 Packet Format 13 2.3.2 Ethernet Frame II 13 2.3.3 IP Packet 15 2.3.4 UDP Datagram 18 2.3.5 Discussion 19 2.4 Audio Signal Processing 20 2.5 Video Signal Processing 21 Chapter 3 FPGA Implementation of the Proposed System 23 3.1 Top Level Module of the Proposed System 23 3.2 The Ethernet Module 25 3.2.1 Overview of the Ethernet Module 25 3.2.2 UDP (receiver, transmitter and CRC32)Module 28 3.2.3 Ethernet FIFO and Payload FIFO 30 3.3 The Audio Module 31 3.3.1 Overview of the Audio Module 31 3.3.2 Controller Module 35 3.3.3 WM8731 Configuration Module 36 3.3.4 Digital Audio Processing Module 37 3.3.5 High Pass Filtering 39 3.3.6 Low Pass Filtering 41 3.3.7 Sound Effect 43 Chapter 4 Experimental Results 47 4.1 Packect Analysis 47 4.1.1 Devices and Environments 47 4.1.2 ARP Response Time 47 4.1.3 Packet Delay Time 48 4.2 Visualization of Audio Signal 48 4.3 Experiment Result of the Proposed System 52 Chapter 5 Conclusion and Future Work 59 References 60 Appendix 62 (a) Derivation of the high pass filtering algorithm 62 (b) Derivation of the low pass filtering algorithm 63 (c) Derivation of the sound effect algorithm 65

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