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研究生： 吳佳璋
Wu, Jia-Jhang
論文名稱： 一個具有無負載架構之低功率高解析度的管線逐漸逼近式類比數位轉換器
A Low Power and High Resolution Pipelined SAR ADC with Loading-Free Architecture
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 121
中文關鍵詞： 電容共享架構 、類比至數位轉換器 、逐漸逼近管線式類比至數位轉換器
外文關鍵詞： Loading-free architecture, ADC, Pipelined SAR ADC
相關次數： 點閱：104  下載：17 
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    • 本論文提出一個具有無負載架構十二位元，每秒八千萬取樣之低功率管線逐漸逼近式類比至數位轉換器。本論文提出的無負載架構概念是將回授電容和第二級逐漸逼近式類比數位轉換器的電容陣列做共用，以達到降低高效能放大器的功率消耗和整體電容面積。此外，針對效能要求較為嚴格的第一級逐漸逼近式類比數位轉換器，本論文採用固定視窗機制去降低功率消耗並改善其非理想效應，例如電容陣列切換時電壓未完全穩定即進行比較造成誤判的問題、電容不匹配造成靜態效能變差、以及比較器的偏移電壓過大造成遺失碼的現象。另外還採用了直接切換技巧去降低介於數位邏輯控制到開關緩衝器的路徑延遲，以提升轉換器的操作速度。
    此類比至數位轉換器是採用台積電90奈米1P9M互補式金氧半製程來實現，電路核心面積為0.117平方毫米，量測到的訊號雜訊失真比為 55.98 分貝，有效位元頻寬為三千五百萬赫茲，總功率消耗為2.72毫瓦。

    This thesis presents a 12-bit 80-MS/s low power pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with loading-free architecture. The basic idea of this work is manipulating the capacitor array of the second-stage SAR ADC to serve as the feedback capacitor of the first stage amplifier during its amplification mode. In addition to the saving in the occupied area of the total capacitor, such an arrangement reduces the power consumption of the used high performance operation amplifier as well, resulting in a low-power and compact ADC. Additionally, the fixed-window function technique is adopted to cut the power consumption and tolerate non-idealities in the first-stage SAR ADC, including the comparator’s erroneous judgments incurred by incomplete settling behavior during the capacitor array switching, large INL/DNL errors due to the capacitor mismatch, and missing codes induced by comparator offset. Moreover, the direct switching technique is also utilized to reduce the critical path delay between the digital control logic and switching buffers.
    This proof-of-concept ADC is fabricated in TSMC standard low-power 90-nm 1P9M CMOS process with the active area of only 0.117 mm2. The measured peak SNDR is 55.98 dB and effective resolution bandwidth (ERBW) is 35 MHz. The total power consumption is 2.72 mW.

    Table of Contents Abstract I Table of Contents VII List of Figures X List of Tables XIV Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 Chapter 2 Fundamentals of Pipelined SAR ADC 6 2.1 PIPELINED SAR ADC 6 2.2 Error Sources in Pipelined SAR ADC 7 2.2.1 Non-idealities of OPAMP-Based Switched Capacitor Circuits 7 2.2.1.1 Finite Gain Error of Op-Amp 7 2.2.1.2 Capacitor Mismatch 11 2.2.1.3 Op-amp Input Offset 13 2.2.1.4 Comparator Offset 16 2.2.1.5 Finite Unity-Gain Frequency 19 2.2.1.6 Memory Effect of Input Sampling 21 2.2.1.7 Effect of Input Sampling Jitter 23 2.2.1.8 Effect of Switch Resistance on MDAC Settling Time 25 2.2.1.9 Op-Amp Induced Noise 28 2.2.2 Non-idealities of Sub-SAR ADC 32 2.2.2.1 Gain Error of the DAC Array 32 2.2.2.2 Incomplete Settling Error 33 2.2.2.3 Switching Noise and KT/C Noise of the DAC Array 36 2.3 ARCHITECTURE TRADE OFFS 38 Chapter 3 12-bit 80-MS/s Pipelined SAR ADC With Loading-Free Architecture 42 3.1 BACKGROUND 43 3.2 MOTIVATION 45 3.3 PROPOSED ADC ARCHITECTURE 47 3.3.1 Overall ADC Architecture 47 3.3.2 Introduction of the Sub-SAR ADC Architecture 51 3.4 DESIGN CONSIDERATIONS OF THE PROPOSED ADC ARCHITECTURE 52 3.4.1 Analysis of MDAC With Loading-Free Architecture 52 3.4.2 Design Considerations of Op-amp Specifications 55 3.4.3 Design Considerations of the Switch Resistance in MDAC 58 3.4.4 Design Considerations in the First Stage Sub-SAR ADC 61 3.4.4.1 Improvement of the Max INL and DNL due to Capacitor Mismatch With Window Function Technique 62 3.4.4.2 Incomplete Settling Tolerance With Window Function Technique 65 3.4.4.3 Power Reduction with Window Function Technique 70 3.5 CIRCUIT IMPLEMENTS 72 3.5.1 Pseudo-Differential Class-AB Telescopic Cascode Operation Amplifier 72 3.5.2 Integrator-Based Common Mode Voltage Stabilization 79 3.5.3 Comparator 80 3.6 LAYOUT AND FLOOR PLAN 83 3.7 SIMULATION RESULTS 89 3.8 EXPERIMENTAL RESULTS 92 3.9 FAULT DIAGNOSIS 95 3.10 SUMMARY 97 Chapter 4 Conclusion and Future Work 98 4.1 CONCLUSION 98 4.2 FUTURE WORK 99 Bibliography 101

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