算術邏輯單元(ALU)及乘法器為中央處理器（CPU）核心元件，負責所有的運算，是中央處理器主要消耗功率元件之一，降低此二部分功率消耗，可有助於降低中央處理器功率消耗。
　　本論文中，我們提出二個低功率設計方法，一為捨棄don’t care狀況，使信號不必分邏輯路徑、加減法路徑，可降低電晶體數量、降低功率消耗、增快速度；二為平衡信號到達輸出點的時間，以降低突波(glitch)的產生，降低功率消耗，同時亦可增快速度。
　　我們應用TSMC 0.25 μm cell去實現新的算術邏輯單元(ALU)及乘法器之核心元件：四對二壓縮器電路，比先前設計有較低的功率消耗和較好的執行效能。

　　The ALU (Arithmetic Logic Unit) and multiplier are main elements of CPU. These perform all the operations required by CPU instructions, and dissipate much of the power consumption in CPU. If we reduce the power consumption of these two elements, we can achieve low power CPU.
　　In this thesis, we present two novel low power methods to implement the ALU and 4-2 compressor which used in multiplier, respectively. One is to abandon the “don’t care” condition in decoder of ALU. This method does not divide signal path into logical and arithmetic paths thus can achieve low power consumption and improve performance by reducing the number of transistors. The other one applied in modified Booth multiplier is using balance delay paths for 4-2 compressor. The glitches generated in our 4-2 compressor can be reduced, thus the power consumption can be reduced. The critical path delay is decreased because the load capacitances of internal nodes are smaller than previous method.
　　Moreover, we use these methods to construct ALU and 4-2 compressor with TSMC 0.25 μm cell library. Experimental results show the new ALU and 4-2 compressor have lower power consumption and higher performance than that of previous ones.

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