電源網路規劃在實體電路設計中成為越來越重要的議題，隨著製程的進步，在晶片裡的電路元件數量快速增加及連線複雜度大幅提升，會導致功率消耗更加嚴重及繞線困難增加。由於電源網路會佔據繞線資源，如果在電路元件擺置與細部繞線完成後，才去調整電源網路是很費時及費力的事情，因此如何在滿足電壓衰退與電遷移效應的限制下預留更多繞線資源，以利繞線階段使用是很重要的。由於早期的研究較少探討符合電壓衰退條件下的電源網路面積如合計算及預留更多繞線資源。因此，本論文提出一個電源網路規劃的流程，其主要分為兩部分，第一部分為提出如何計算在符合電壓衰退條件下的電源網路面積，第二部分則提出混合基因暨模擬退火法來調整電源限段之線寬及選擇更好的擺放位置，以達到更好的可繞度。實驗結果證明本論文的方法可以在符合電壓衰退條件下提升繞線階段的可繞度。

Powerplanning is a crucial stage in the physical design. Due to advance in manufacture technology, the number of transistors in a chip increases dramatically which leads to higher power consumption and makes routing more difficult. Since a power network will occupy routing resource, it is very important to reduce routing area while satisfying IR-drop and electromigration constraint. However, most of previous works only minimize power routing area without considering routing congestion. Hence, in this thesis, we want to propose a powerplanning methodology which can consider routing congestion while satisfying IR-drop and electromigration constraint. Our powerplanning flow can be divided into two parts. The first part applies the bisection method to calculate proper area required for power stripes for satisfying IR-drop constraint. In the second part, we propose the hybrid GA-SA based algorithm to adjust widths of power stripes and search better positons of power stripes. The experimental results show that our method not only can satisfy the IR-drop constraint but also lead to higher routability.

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