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研究生: 王瑞麟
Wang, Jui-Lin
論文名稱: 數位音訊廣播接收器中通道解碼及音訊解碼之共用管線式電路設計
Circuit Sharing of OFDM and IMDCT by Modified Pipeline FFT Processor for DAB Receiver
指導教授: 戴顯權
Tai, Shen-Chuan
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2002
畢業學年度: 90
語文別: 英文
論文頁數: 77
中文關鍵詞: 正交分頻多工反向修正離散餘弦轉換數位音訊廣播
外文關鍵詞: OFDM, DAB, IMDCT
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  • 本論文針對數位音訊廣播接收器,採用一個快速演算法,將反向修正離散餘弦轉換(IMDCT)的執行次數降低。相較於其它的快速演算法,我們所提出的方法,可以利用電路分享(Circuit Sharing)的技術輕易的將通道解碼的正交分頻多工(OFDM) 和IMDCT結合共用,以符合數位音訊廣播接收器朝低成本,高整合的趨勢
    若和未使用電路分享的方法比較,本設計減少近乎一個IMDCT電路的面積。除此之外,另利用正交分頻多工(OFDM)係數的對稱性,將儲存其值的唯讀記憶體面積減少一半。
    在電路架構上,本設計採用單一管線式處理單元,它只包含一個乘法器、一個加法器和一個減法器;並在每四個週期,就算出一筆蝴蝶結運算,以達到低面積高速度的設計要求。
    最後,在單一管線式處理單元的模組基礎上,利用上述電路分享的方法,實現供通道解碼及音訊解碼所共用的電路。

    In this Thesis, a fast implementation algorithm for inverse modified discrete cosine transform (IMDCT), stated as a 32*64 matrix operation in the DAB receiver is adopted. Comparing to the existed fast algorithm, this fast algorithm is easy to achieve the function of circuit sharing of combining the fast Fourier transform (FFT) circuit in the orthogonal frequency division multiplexing (OFDM) with synthesis filter in the audio decoder to achieve a highly integrated, low gate count and small ROM size DAB receiver.
    Verse a not circuit-sharing approach, the design here saves almost an IMDCT circuit. In addition to this, the size of memory for storing 2048-points FFT (OFDM) coefficients is further reduced from 1024 to 512 by using symmetric property of twiddle coefficient.
    The design applies pipeline architecture to the butterfly unit. It consists of only one multiplier, one adder, and one subtractor. At the same time, it is capable of computing one butterfly computation every 4 cycles. Then the circuit meets the low area and high speed requirement for DAB receiver.
    Finally, we implement the IMDCT and the OFDM circuit that is based on the circuit sharing method by single process element with pipeline structure for DAB receiver.

    CONTENTS List of Figures vi List of Tables viii Chapter 1. Introduction 1 1.1 Background 1 1.2 Outline of This Thesis 3 Chapter 2. DAB System 4 2.1 Overview of DAB 4 2.1.1 System Concept 4 2.1.2 Transmission Mode and Frame 5 2.1.3 Single Frequency Network (SFN) 8 2.1.4 Error Correction 9 2.2 OFDM Modulation and Demodulation 11 2.3 ISO/MPEG Audio CODEC 14 2.3.1 Simultaneous and Non-Simultaneous Masking 14 2.3.2 Psychoacoustic Coding 15 2.3.3 ISO/MPEG Audio Layer Models 16 2.3.4 Layer I and Layer II 17 2.3.5 Audio Framing Format 19 Chapter 3. Circuit-Sharing Scheme 21 3.1 Polyphase and Cosine Modulated Filter Banks 21 3.1.1 Polyphase Representation 21 3.1.2 Cosine Modulated Filter Banks 23 3.2 Filter Bank in MPEG-1 Audio 25 3.3 Fast Synthesis Filter 28 3.1.1 IMDCT by DCT 28 3.1.1 DCT by FFT 29 3.4 Proposed Method for Circuit Shring 34 Chapter 4. Hardware Design of Circuit-Sharing 36 4.1 Architecture for Modified FFT Processor 36 4.2 The Modified FFT Processor for Circuit-Sharing in DAB Receiver 40 4.2.1 Interface Unit 41 4.2.2 Address Generation Unit 42 4.2.3 ROM-Sharing Unit 47 4.2.4 Processing Element 48 4.3 Practical Issues of Implementation 57 Chapter 5. Verification and Comparison 59 5.1 Verification of the IMDCT by FFT in Matlab 59 5.2 Circuit-Sharing Scheme Comparison 62 5.3 Gate Count Comparison 63 5.4 Timing Diagram 64 Chapter 6. Conclusion and Future Work 71 Reference 73 List of Figures Figure 2.1 Overview of DAB system 4 Figure 2.2 DAB transmission frame 6 Figure 2.3 Phase change in symbols 7 Figure 2.4 Symbol structure for mode I 8 Figure 2.5 Long distance multipath 9 Figure 2.6 Viterbi data generation 10 Figure 2.7 Direct and indirect wave travel over different paths 11 Figure 2.8 Signal in multipath 11 Figure 2.9 OFDM and the orthogonality principle 12 Figure 2.10 Time to frequency by sine wave 12 Figure 2.11 Fast Fourier transform 13 Figure 2.12 Simultaneous masking 15 Figure 2.13 Non-simultaneous masking 15 Figure 2.14 Psychoacoustic coder 16 Figure 2.15 MPEG-1 audio modes 17 Figure 2.16 Layer I and layer II coding model 19 Figure 2.17 Layer I and layer II framing format 20 Figure 3.1 Polyphase implementation 23 Figure 3.2 Magnitude response of the prototype and their cosine modulated version 24 Figure 3.3 Analysis filter flow (I) 26 Figure 3.4 Analysis filter flow (II) 26 Figure 3.5 Synthesis filter flow 27 Figure 3.6 64-points IMDCT by 32-points DCT data flow 33 Figure 3.7 32-points DCT by 32-points FFT data flow 33 Figure 3.8 Modified synthesis filter flow 35 Figure 4.1 Single process architecture 37 Figure 4.2 Data format of IMDCT complex sample 38 Figure 4.3 Data format of OFDM complex sample 38 Figure 4.4 Data format of twiddle coefficient complex sample 38 Figure 4.5 8-points DIF FFT data flow 39 Figure 4.6 Block diagram of whole circuit 40 Figure 4.7 Circuit-sharing flow chart 42 Figure 4.8 Block diagram of address generation unit 43 Figure 4.9 ROM-sharing circuit 47 Figure 4.10 Butterfly operation 49 Figure 4.11 Processing element circuit 52 Figure 4.12 Pipeline PE data flow 56 Figure 4.13 Schematic diagram of whole circuit 57 Figure 4.14 Final physical layout of the modified FFT processor 58 Figure 5.1 Timing diagram 64 List of Tables Table 2.1 DAB transmission mode 5 Table 2.2 Data by phase 7 Table 2.3 MPEG-1 audio support 16 Table 2.4 MPEG-1 audio layer 17 Table 2.5 Changes between DAB and MPEG audio 20 Table 4.1 The relationship between modes and control signals 41 Table 4.2 Binary representation of the base index in a 2048-points FFT 44 Table 4.3 Binary representation of the base index in post-multiply 45 Table 4.4 The relationship between stage counter and increment 46 Table 4.5 Butterfly PE sequence for OFDM and FFT of IMDCT 50 Table 4.6 Butterfly PE sequence for post-multiply of IMDCT 51 Table 5.1 IMDCT by FFT verification by Matlab 59 Table 5.2 Comparison of Different Circuit-Sharing for IMDCT Operation 62 Table 5.3 Gate count comparison between FFT and circuit-sharing 63

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