矽穿孔在三維積體電路中扮演著相當重要的角色，其藉由提供層與層之間的垂直連線來達到降低繞線面積及增加接線頻寬的效果。因此有效率測試矽穿孔能否正常運作是在三維積體電路設計上的一個相當重要的目標。此論文主要目的在於測試及診斷堆疊後矽穿孔上面的串音干擾，並且可針對不同的串音干擾影響範圍及正方形與六邊形的矽穿孔排列布局提出一個分組演算法，使越多的矽穿孔能夠同時被測試及診斷。基於矽穿孔分組演算法的結果，我們亦實現了一個高效能、低面積消耗之矽穿孔測試及診斷架構，其架構重複利用了現存且在堆疊前常使用的IEEE 1149.1, IEEE 1500等測試標準之邊界掃描電路元件以降低測試及診斷電路之面積需求。實驗結果顯示出此論文之電路架構基於低面積消耗下亦具有低測試及診斷時間之成果。

Through Silicon Vias (TSVs) play an important role in 3D chip integration. By providing vertical interconnection, routing area can be decreased and bandwidth can be increased. Effective and efficient testing for correct operation of TSVs is essential for 3D IC design. This work addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously. Based on the results of the TSV grouping, we implement a high-efficiency, low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for pre-bond testing. Experimental results show the low test and diagnosis time as well as the low area overhead of the proposed test architecture.

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