本論文為應用在5G通訊技術裡3.4~3.6 GHz Sub-6G頻段的非整數型鎖相迴路電路設計，主要分為兩大部分:第一部分為壓控振盪器的模擬設計，主要的目的是為了優化鎖相迴路的動態響應，設計出符合鎖相迴路使用的子電路壓控振盪器。為了改善壓控振盪器增益跳動過大造成鎖相迴路不好的動態響應，加入可變電容陣列來重新定義調變容值的範圍，讓其容值變化不那麼劇烈並且更加線性。在模擬設計後，等效容值可調範圍為1.03~1.78 pF。LC壓控振盪器的頻率可調範圍為3.275~3.677 GHz (11.56%)，在頻率偏移1 MHz時最好的相位雜訊為-120.58 dBc/Hz。模擬整體壓控振盪器的消耗功率為12.53 mW，輸出功率皆大於-3 dBm。第二部分為3.4~3.6 GHz非整數型鎖相迴路設計與整合，其中子電路包含相位頻率偵測器(PFD)、充電泵(CP)、低通迴路濾波器(LPF)、壓控振盪器(VCO)與除頻器(Divider)，其中除頻器又包含前置除頻器(Prescaler)、多模數除頻器(Multi-modulus Divider)與兩級的三角積分調變器(Delta-Sigma Modulator)。在非整數型鎖相迴路的量測上，輸入參考頻率為26.86 MHz，輸出頻率範圍為3.438~3.612 GHz，相位雜訊在頻率偏移1 MHz時最好的為-96.85 dBc/Hz，輸出功率皆大於-7 dBm，整體功率消耗為19.56 mW，晶片面積為1.539 。非整數型鎖相迴路主要的優點是，可以在達到輸出頻率解析度高的同時，頻寬不受參考頻率影響，因此在決定迴路頻寬大小時可以比較彈性，對於雜訊與鎖定時間的設計考量，會有比較充裕的設計選擇。

This thesis proposes a fractional-N phase-locked loop circuit design applied in the 3.4~3.6 GHz Sub-6G frequency band in 5G communication applications. It is mainly divided into two parts. The first part is the design of the voltage-controlled oscillator. The main purpose is to design a sub-circuit voltage-controlled oscillator that is suitable for the phase-locked loop and to prepare the optimization work of the PLL. In order to improve the bad dynamic response of the phase-locked loop caused by the excessive gain jump of the voltage-controlled oscillator, a varactor array is added to redefine the range of the modulation capacitance, so that its vco gain change is not so drastic and become more linear. After the simulation design, the adjustable range of the equivalent capacitance is from 1.03 to 1.78 pF, and the adjustable frequency range of the LC voltage-controlled oscillator is from 3.275 to 3.677 GHz (11.56% ,tuning ratio). The best phase noise is -120.58 dBc/Hz when the frequency offset is 1 MHz from the center frequency of 3.275 GHz. The simulated overall VCO power consumption is 12.53 mW, and the output power is greater than -3 dBm. The second part of this thesis is the integration design of a 3.4~3.6 GHz fractional-N phase-locked loop, in which the sub-circuits of it include a phase frequency detector(PFD), a charge pump(CP), a low-pass loop filter(LPF), a voltage-controlled oscillator(VCO) and a frequency divider(FD). The frequency divider includes a prescaler, a multi-modulus frequency divider and a two-stage Delta-Sigma modulator. In the measurement of this designed fractional-N PLL, the input reference frequency is 26.86 MHz, the output frequency range is from 3.438 to 3.612 GHz. The available phase noise is -96.85 dBc/Hz at 1 MHz offset from center frequency of 3.505 GHz. The output power is greater than -7 dBm. The overall power consumption is 19.56 mW and the chip area is 1.539 . The main advantage of the fractional-N phase-locked loop is that it can achieve high resolution of the output frequency while the bandwidth is not affected by the reference frequency. Therefore, fractional-N PLL can be more flexible when determining the bandwidth of the loop. For the design considerations of noise and lock time, there will be more design choices.

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