隨著邏輯元件尺寸的持續縮小邁入至10奈米的節點後，矽半導體元件因受限於電子遷移率、發光效率與環境溫度等限制，難以滿足現今元件特性需求。因此，尋找下一世代半導體材料並研究其相關製程成為突破傳統矽半導體因自身發展侷限和摩爾定律限制的首要任務。有鑒於此，本論文旨在研究半導體高移動率新型材料-矽鍺化合物半導體，並以兩種新穎退火技術 – 高壓退火技術及低溫微波退火技術及金屬矽化物製程探討在源極/汲極上之影響。
微波退火技術是一種以微波直接穿透晶格，直接對原子晶格震動加熱以利其吸收能量，因而可以免除高溫熱傳導使摻雜物質擴散之效應，達到低溫退火的目的。然而高壓退火技術則是藉由原子因高壓而抑制摻雜物質大幅擴散，並且因高壓而降低退火溫度但不影響活化能力。在本論文的第一部分，利用高壓退火技術及微波退火技術來活化多晶鍺薄膜中的離子佈植摻雜物，探討硼離子或磷離子經由退火後之擴散情況，藉此達到低阻值。
第二部分探討不同比例之矽鍺薄膜經硼離子佈值及熱退火(高壓退火及低能量微波退火)對於應力及載子活化之影響。經量測結果我們發現，使用低能量微波退火的矽鍺薄膜比高壓退火展現出較低的阻值、較小的佈值缺陷厚度及最好的殘留應力指數，但差距不大。然而所有低能量微波退火的樣品中，所屬矽鍺比8:2經3P (1P=600W)的結果為最佳。這些結果說明了高壓退火及低熱預算的微波退火方式皆有助於新型材料矽鍺的載子活化，同時也證明了兩種新穎退火方式皆能夠維持矽鍺間之應力。
隨著半導體尺寸的微縮，源極/汲極上的金屬接觸電阻率也隨之的上升，使的整體的阻值無法下降，導致元件的性能無法提升。因此，金屬矽化物成為降低金屬接觸電阻的重要因素之一。在本論文的第三部分，嘗試使用新的材料-鈀來獲得低薄層電阻，高熱穩定性，低溫形成矽化物，低電阻率，高濃度摻雜等等使源極/汲極的肖特基勢壘降低。實驗結果顯示，高壓熱退火技術溫度介於300 ℃ ~ 400 ℃形成矽化鈀的熱穩定度高，但是當溫度提升至500 ℃時則會出外擴散的現象。而低溫微波退火在3P至5P皆形成矽化鈀且較高壓退火穩定。然而矽化鈀薄膜經由熱退火處理後阻值皆上升因為金屬團聚效應導致薄膜粗糙度上升，導致接觸面為非連續性平面。

As the size of logic semiconductor continues to shrink to 10 nanometers, the silicon-based semiconductor components are limited by electron mobility, luminous efficiency, and ambient temperature, making it difficult to meet today's device performance. Therefore, finding the next generation of semiconductor materials and studying their related processes has become the primary task of breaking through the limitations of traditional semiconductors due to their own development limitations and Moore's Law. According to this situation, this thesis aims to study the novel material (silicon-germanium compound), which is the high-mobility compound semiconductor, and discuss the influence on the source/drain by high pressure annealing technology and low-temperature microwave annealing technology, and metal silicide process.
Microwave annealing technology is to directly penetrate the crystal lattice by microwave and directly vibrate the atomic lattice to absorb energy than heating up. Therefore, the effect of high-temperature heat conduction to diffuse the dopant can be eliminated, and the purpose of low-temperature annealing can be achieved. High pressure annealing technology is using high pressure to compression the lattice thus to suspended the dopant diffusion, and the high pressure actuate the processing temperature decrease, therefore achieve low-temperature annealing. In the first part of this thesis, we have studied doping profiles, activation ability, and defect annealing of B and P introduced in Ge by ion implantation at 5E15 cm3 and 10 keV, and annealed under various conditions by high pressure annealing and microwave annealing.
In the second part of this thesis, the effects of dopant implantation and thermal annealing (high pressure annealing and low energy microwave annealing) on stress and dopant activation of silicon-germanium layer are investigated. Through the results, we found that the low-energy microwave annealed silicon-germanium film exhibited lower resistance, the thinner thickness of ion implant defect and the best residual stress index but only little bit better than high pressure annealing. However, in all low-energy microwave annealed samples, the results of the silicon germanium ratio of 8:2 via 3P (1P = 600W) were optimal. These results indicate that the high pressure annealing and microwave annealing with low thermal budget contributes to the dopant activation on silicon-germanium and proves the two novel annealing technologies are both good to maintain the stress between silicon and germanium.
As the size of the semiconductor shrinks, the metal contact resistivity on the source/drain also increases, resulting in an inability to improve the performance of the device. Therefore, metal silicide is one of the important factors for reducing metal contact resistance. The third part of this thesis tries to use the new material - palladium to obtain low sheet resistance, high thermal stability, low formation temperature, low contact resistivity, high concentration doping, etc. to lower the Schottky barrier on the source/drain. The results show that thermal stability of palladium silicide is high while the heat treatment temperature is by high pressure annealing between 300 °C and 400 °C, but when the temperature raised to 500 °C, it will start to diffuse. Nevertheless, annealed by microwave annealing is more stable than high pressure annealing.

[1] G. E. Moore, "Progress in digital integrated electronics [Technical literature, Copyright 1975 IEEE. Reprinted, with permission. Technical Digest. International Electron Devices Meeting, IEEE, 1975, pp. 11-13.], IEEE Solid-State Circuits Society Newsletter, vol. 20, pp. 36-37, 2006.
[2] D. R. H, G. F. H, Y. U. H. N, R. V. Leo, B. E, and L. A. R, “Design of ion-implanted MOSFET's with very small physical dimensions,” IEEE Solid-State Circuits Society Newsletter, vol. 12, pp. 38-50, 2007.
[3] C.M. Osburn and K.R. Bellur, “Low parasitic resistance contacts for scaled ULSI devices”, Thin Solid Films, Vol. 332, pp. 428-436, 1998.
[4] J.A. Kittl et al., “Silicides and germanides for nano-CMOS applications”, Materials Science and Engineering B, Vol. 154-155, pp. 144-154, 2008.
[5] X. Qiuxia et al., “Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs”, IEEE Transactions on Electron Devices, Vol. 54, pp. 1394-1401, 2007.
[6] C. Ortolland et al., “Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology”, Symposium on VLSI Technology, 2009.
[7] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices: Cambridge University Press, 2009.
[8] Y. Song, H. Zhou and Q. Xu, “Source/drain technologies for the scaling of nanoscale CMOS device”, Solid State Sciences, Vol. 13, pp. 294-305, 2011.
[9] P.A. Stolk, H.J. Gossmann, D.J. Eaglesham and J.M. Poate, “Implantation and transient boron diffusion: the role of the silicon self-interstitial”, Nuclear Instruments and Methods in Physics Research Section B, Vol. 96, pp. 187-195, 1995.
[10] V. E. Boeisenko and S. G. Yudin, “Steady‐state solubility of substitutional impurities in silicon”, Physica Status Solidi (a), Vol. 101, pp. 123-127, 1987.
[11] E. J. H. Collart et al., “Co-implantation with conventional spike anneal solutions for 45nm n-type metal-oxide-semiconductor ultra-shallow junction formation”, Journal of Vacuum Science & Technology B, Vol. 24, pp. 507-509, 2006.
[12] N. Cagnat, C. Laviron, D. Mathiot, C. Rando and M. Juhel, “Shallow Junction Engineering by Phosphorus and Carbon Co-implantation: Optimization of Carbon Dose and Energy”, 2007 Materials Research Society international conference, pp. 217-222, 2007.
[13] B. J. Pawlak et al., “Suppression of phosphorus diffusion by carbon co-implantation”, Applied Physics Letters, Vol. 89, pp. 062102, 2006.
[14] S. B. Felch et al., “Ultrashallow junctions formed by C coimplantation with spike plus submelt laser annealing”, Journal of Vacuum Science & Technology B, Vol. 26, pp. 281-285, 2008.
[15] Y. Sasaki et al., “B2H6 plasma doping with “in-situ He pre-amorphization””, 2004 Symposium on VLSI Technology, pp. 180-181, 2004.
[16] Y. Sasaki et al., “Conformal Doping for FinFETs and Precise Controllable Shallow Doping for Planar FET Manufacturing by a Novel B2H6/Helium Self-Regulatory Plasma Doping Process”, 2008 IEEE International Electron Devices Meeting, pp. 917-920, 2008.
[17] K. Adachi et al., “Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond”, 2006 Materials Research Society international conference, pp. 149-158, 2006.
[18] T. Ito et al., “10-15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing”, Japanese Journal of Applied Physics, Vol. 41, pp. 2394-2398, 2002.
[19] S.H. Jain et al., “Metastable boron active concentrations in Si using flash assisted solid phase epitaxy”, Journal of Applied Physics, Vol. 96, pp. 7357-7360, 2004.
[20] S.H. Jain et al., “Low resistance, low-leakage ultrashallow p+-junction formation using millisecond flash anneals”, IEEE Transactions on Electron Devices, Vol. 52, pp. 1610-1615, 2005.
[21] H. Kiyama, “Flash Lamp Annealing Latest Technology for 45nm device and Future devices”, 14th International Conference on Advanced Thermal Processing of Semiconductors, pp. 65-71, 2006.
[22] J. Foggiato and W.S. Yoo, “Implementation of flash technology for ultra shallow junction formation: challenges in process integration”, Journal of Vacuum Science & Technology B, Vol. 24, pp. 515-520, 2006.
[23] C.H. Poon, B.J. Cho, Y.F. Lu, M. Bhat and A. See, “Multiple-pulse laser annealing of preamorphized silicon for ultrashallow boron junction formation”, Journal of Vacuum Science & Technology B, Vol. 21, pp. 706-709, 2003.
[24] A. Shima and A. Hiraiwa, “Ultra-shallow junction formation by non-melt laser spike annealing and its application to complementary metal oxide semiconductor devices in 65-nm node”, Japanese Journal of Applied Physic, Vol. 45, pp. 5708-5715, 2006.
[25] K.J. Kuhn, “Considerations for ultimate CMOS scaling”, IEEE Transactions on Electron Devices, Vol. 59, pp. 1813-1828, 2012.
[26] H.R. Harris et al., “Band-engineered low pMOS VT high-k/metal gates featured in dual channel CMOS integration scheme”, 2007 IEEE Symposium on VLSI Technology, pp. 154-155, 2007.
[27] J. Mitard et al., “High-mobility 0.85 nm-EOT Si0.45Ge0.55-pFETs: delivering high performance at scaled VDD”, 2010 International Electron Devices Meeting, pp. 10.6.1-4, 2010.
[28] J. Welser, J.L. Hoyt and J.F. Gibbons, “Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors” IEEE Electron Device Letters, Vol. 15, pp. 100-102, 1994.
[29] J. Welser, J.L. Hoyt, S. Takagi and J.F. Gibbons, “Strain dependence of the performance enhancement in strained-Si n-MOSFETs” IEEE International Electron Devices Meeting, pp. 373-376, 1994.
[30] S. Thompson et al., “A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 um2 SRAM Cell”, IEEE International Electron Devices Meeting, pp. 3.2.1-4, 2002.
[31] Ji-Song Lim, S.E. Thompson and J.G. Fossum, “Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs” IEEE Electron Device Letters, Vol. 25, pp. 731-733, 2004.
[32] S. E. Thompson and G. Sun, ”Strained Si and the future direction of CMOS”, International Symposium on VLSI Technology, Systems, and Applications, pp. 1-4, 2006.
[33] A. Renau, “Device performance and yield - A new focus for ion implantation”, IEEE International Workshop on Junction Technology, pp. 1-6, 2010.
[34] F. A. Khaja et al., “Schottky barrier height tuning using P+ DSS for NMOS contact resistance reduction”, AIP Conference Proceedings, Vol. 1496, pp. 42-45, 2012.
[35] K. V. Rao et al., “NMOS contact resistance reduction with selenium implant into NiPt silicide”, AIP Conference Proceedings, Vol. 1496, pp. 46-49, 2012.
[36] C.-N. Ni et al., “Laser anneal assisted contact resistivity reduction with post-silicide implantation for 14nm node and beyond”, VLSI-TSA, 2013.
[37] T. Ghani et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, IEEE International Electron Devices Meeting, pp. 978, 2003.
[38] S. E. Thompson et al., “A 90-nm logic technology featuring strained-silicon”, IEEE Transaction on Electron Devices, Vol. 51, pp. 1790, 2004.
[39] C. H. Jan et al., “A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors”, International Electron Devices Meeting, pp. 60, 2005.
[40] G. Moore, “Excerpts from a conversation with Gordon Moore: Moore’s Law”, Video Transcript, Intel, 2005. 54.
[41] T. L. Shih, Y. H. Su and W. H. Lee, “High dopant activation of phosphorus in Ge crystal with high-temperature implantation and two-step microwave annealing”, Applied Physics Letters, Vol. 109, pp. 122103, 2016.
[42] Y. Taur and T.H. Ning, “Fundamentals of modern VLSI devices”, 2013.
[43] R.H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE Journal of Solid-State Circuits, Vol. 9, pp. 256-268, 1974.
[44] M. Kumar, “Effects of Scaling on MOS Device Performance”, IOSR Journal of VLSI and Signal Processing, Vol. 5, pp. 25-28, 2015.
[1] E. Thostenson and T.-W. Chou, “Microwave processing: fundamentals and applications”, Composites Part A: Applied Science and Manufacturing, Vol. 30, pp. 1055-1071, 1999.
[2] A. Metaxas, “Foundations of electroheat: a unified approach”, John Wiley & Sons Inc, 1996.
[3] D. Stuerga, “Microwave-material interactions and dielectric properties, key ingredients for mastery of chemical microwave processes”, Microwaves in Organic Synthesis (Loupy A, ed). 2nd ed. Weinheim, Germany: Wiley-VCH Verlag Gmbh & Co. KgaA, pp. 1-61, 2006.
[4] H. Fröhlich, “Theory of dielectrics”, 1949.
[5] G. G. Raju, “Polarization and static dielectric constant”, Dielectrics in electric fields, Vol. 19, 2003.
[6] P. Lidström, J. Tierney, B. Wathey, and J. Westman, “Microwave assisted organic synthesis—a review”, Tetrahedron, Vol. 57, pp. 9225-9283, 2001.
[7] W. Jung, A. Misiuk and D. Yang, “Effect of high pressure annealing on electrical properties of nitrogenand germanium doped silicon”, Nuclear Instruments and Methods in Physics Research Section B, Vol. 253, pp. 214-216, 2006.
[8] K. Ueda and M. Kasu, “High-pressure and high-temperature annealing effects of boron-implanted diamond”, Diamond and Related Materials, Vol. 17, pp. 502-505, 2008.
[9] F. F. Morehead and R. F. Lever, “Enhanced “tail” diffusion of phosphorus and boron in silicon: Self‐interstitial phenomena”, Applied physics letters, Vol. 48, pp. 151, 1986.
[10] A. E. Michel, W. Rausch, P. A. Ronsheim and R. M. Kastl, “Rapid annealing and the anomalous diffusion of ion implanted boron into silicon “, Applied physics letters, Vol. 50, pp. 416, 1987.
[11] P. M. Fahey, P. B. Griffin and J. D. Plummer, “Point defects and dopant diffusion in silicon”, Reviews of modern physics, Vol. 61, pp. 289, 1989.
[12] R. B. Fair, “Point Defect Charge‐State Effects on Transient Diffusion of Dopants in Si”, Journal of The Electrochemical Society, Vol. 137, pp. 667, 1990.
[13] M. Kumar, “Effects of Scaling on MOS Device Performance”, IOSR Journal of VLSI and Signal Processing, Vol. 5, pp. 25-28, 2015.
[14] S. Oktyabrsky and P. D. Ye, “Fundamentals of III-V Semiconductor MOSFETs”, Springer, 2010.
[15] International Technology Roadmap for Semiconductors, Vers. 2.0, 2015.
[16] C.W. Leitz, “High mobility strained Si/SiGe heterostructure MOSFETs: channel engineering and virtual substrate optimization”, Massachusetts Institute of Technology, 2002.
[17] J. Park et al., “Comparison of ultralow-energy ion implantation of boron and BF2 for ultrashallow p+/n junction formation”, Applied physics letters, Vol. 74, pp. 1248-1250, 1999.
[18] G. Impellizzeri et al., “Fluorine counter doping effect in B-doped Si”, Applied Physics Letters, Vol. 91, pp. 132101, 2007.
[19] D. A. Neamen, “Semiconductor physics and devices”, Mc Graw Hill, 2012.
[20] C. Y. Chang and Y. K. Fang, “Specific contact resistance of metal-semiconductor barriers”, Solid-State Electronics, Vol. 14, pp.541-550, 1971.
[21] K. Barmak and K. Coffey, “Metallic films for electronic, optical and magnetic application”, Woodhead Publishing, pp. 656, 2014.
[1] Y. C. Yeo et al., “Germanium-based transistors for future high performance and low power logic applications”, IEEE International Electron Devices Meeting, pp. 2.4.1-2.4.4, 2015.
[2] C. Lu et al., “Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT”, Symposium on VLSI Technology, pp. T18-T19, 2015.
[3] Y. C. Fu et al., “High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response”, IEEE International Electron Devices Meeting, pp. 18.5.1-18.5.4, 2010.
[4] L. Witters et al., “trained germanium quantum well p-FinFETs fabricated on 45 nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect”, Symposium on VLSI Technology, pp. T56-T57, 2015.
[5] H. Wu et al., “First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters”, IEEE International Electron Devices Meeting, pp. 2.1.1-2.1.4, 2015.
[6] Y. J. Lee et al., “Full low temperature microwave processed Ge CMOS achieving diffusion-less junction and ultrathin 7.5 nm Ni mono-germanide”, IEEE International Electron Devices Meeting, pp. 23.3.1-23.3.4, 2012.
[7] J. Mitard et al., “First demonstration of 15 nm-WFIN inversionmode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe source/drain”, IEEE International Electron Devices Meeting, pp. 16.5.1-16.5.4, 2014.
[8] R. Duffy and M. Shayesteh, “Novel processing for access resistance reduction in germanium devices”, International Workshop on Junction Technology, pp. 1-6, 2014.
[9] M. J. H. Van Dal et al., “Germanium n-channel planar FET and FinFET: Gate-stack and contact optimization”, IEEE Transactions on Electron Devices, Vol. 62, pp. 3567-3574, 2015.
[10] A. Chroneos and H. Bracht, “Diffusion of n-type dopants in germanium”, Applied Physics Reviews, Vol. 1, pp. 011301, 2014.
[11] S. Uppal et al., “Diffusion of boron in germanium at 800–900°C”, Journal of Applied Physics, Vol. 96, pp. 1376, 2004.
[12] S. Uppal et al., “Ion-implantation and diffusion behaviour of boron in germanium”, Physica B: Condensed Matter, Vol. 308-310, pp. 525-528, 2001.
[13] K. C. Jones and E. E. Haller, “Ion implantation of boron in germanium”, Journal of Applied Physics, Vol. 61, pp. 2469, 1987.
[14] Y. S. Suh et al., “Modeling of boron and phosphorus implantation into (100) Germanium”, IEEE Transactions on Electron Devices, Vol. 52, pp. 91, 2005.
[15] C. O. Chui et al., “Activation and diffusion studies of ion-implanted p and n dopants in germanium”, Applied Physics Letter, Vol. 83, pp. 3275, 2003.
[16] A. Satta et al., “P implantation doping of Ge: Diffusion, activation, and recrystallization”, Journal of Vacuum Science & Technology B, Vol. 24, pp. 494, 2006.
[17] Y. L. Chao and J. C. S. Woo, “Germanium n+/p diodes: A dilemma between shallow junction formation and reverse leakage current control”, IEEE Transactions on Electron Devices, Vol. 57, pp. 665-670, 2010.
[18] G. Hellings et al., “Ultra shallow arsenic junctions in germanium formed by millisecond laser annealing”, Electrochemical and Solid-State Letters, Vol. 14, pp. H39-H41, 2011.
[19] C. Wündisch et al., “Millisecond flash lamp annealing of shallow implanted layers in Ge”, Applied Physics Letters, Vol. 95, pp. 252107, 2009.
[20] Y. Wang et al., “Laser spike annealing for n-type Ge junction & Ti silicide formation”, International Workshop on Junction Technology, pp. 1-4, 2014.
[21] G. Thareja et al., “High performance germanium N-MOSFET with antimony dopant activation beyond 1 × 1020 cm−3”, IEEE International Electron Devices Meeting, pp. 10.5.1-10.5.4, 2010.
[22] M. Shayesteh et al., “Optimized laser thermal annealing on germanium for high dopant activation and low leakage current”, IEEE Transactions on Electron Devices, Vol. 61, pp. 4047-4055, 2014.
[23] H. Miyoshi et al., “In-situ contact formation for ultra-low contact resistance NiGe using carrier activation enhancement (CAE) techniques for Ge CMOS”, IEEE Transactions on Electron Devices, pp. 1-2, 2014.
[24] Donald A. Neamen, “Semiconductor Physics and Devices Basic Principles”, Chapter.4, 2003.
[25] N. Kh. Abrikosov et al., “Individual and joint solubilities of aluminum and phosphorus in germanium and silicon”, Russian Journal of Inorganic Chemistry, Vol. 7, pp. 429, 1962.
[26] W.-H. Lee et al., “Studies on ultra shallow junction 20nm P-MOS with 250°C microwave annealing for activation of boron dopants in silicon”, 20th International Conference on Ion Implantation Technology, 2014.
[27] A. Satta et al., “Diffusion, activation, and recrystallization of boron implanted in preamorphized and crystalline germanium”, Applied Physics Letters, Vol. 87, pp. 172109, 2005.
[28] W. Hsu et al., “Diffusion and recrystallization of B implanted in crystalline and pre-amorphized Ge in the presence of F”, Journal of Applied Physics, Vol. 120, pp. 15701, 2016.
[1] D. Vogler, “The Roadmap to 5nm: Convergence of Many Solutions Needed”, SEMICON West, 2015.
[2] G. V. Luong et al., “Study of dopant activation in biaxially compressively strained SiGe layers using excimer laser annealing”, Journal of Applied Physics, Vol. 113, pp. 204902, 2013.
[3] R. A. Minamisawa et al., “p-type ion implantation in tensile Si/compressive Si0.5Ge0.5/tensile strained Si heterostructures”, Journal of The Electrochemical Society, Vol. 159, pp. H44-H51, 2011.
[4] B. Holländer et al., “Strain relaxation of pseudomorphic Si1− xGex ∕ Si (100) heterostructures after Si+ ion implantation”, Journal of applied physics, Vol. 96, pp. 1745-1747, 2004.
[5] D. Buca et al., “Si+ ion implantation for strain relaxation of pseudomorphic Si1−xGex ∕ Si (100) heterostructures”, Journal of applied physics, Vol. 105, pp. 114905, 2009.
[6] H. Chen et al., “Crosshatching on a SiGe film grown on a Si (001) substrate studied by Raman mapping and atomic force microscopy”, Physical Review B, Vol. 65, pp. 233303, 2002.
[1] S.-D. Kim, “Optimum location of silicide/Si interface in ultra-thin body SOI MOSFETs with recessed and elevated silicide source/drain contact structure”, Solid-State Electronics, Vol. 53, pp. 1112-1115, 2009.
[2] L. Wilson, “International technology roadmap for semiconductors”, Semiconductor Industry Association, Washington, DC, USA, 2013.
[3] T. Ghani et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” IEEE Electron Devices Meeting, pp. 978-980, 2003.
[4] G. Yeric, “Moore’s law at 50: Are we planning for retirement?”, IEEE Electron Devices Meeting, pp. 1-8, 2015.
[5] H. Yu et al., “1.5×10-9 Ω·cm2 Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation”, IEEE Electron Devices Meeting, pp. 592, 2015.
[6] Zhang C.-N. Ni et al., “Ultra-Low Contact Resistivity with Highly Doped Si:P Contact for nMOSFET”, Symposium on VLSI Technology, pp.T118, 2015.
[7] Z. Zhang et al., “Ultra Low Contact Resistivities for CMOS Beyond 10-nm Node”, IEEE Electron Device Letters, Vol. 34, pp. 723, 2013.
[8] P. Raghavan et al., “Holisitic device exploration for 7nm node,” IEEE Custom Integrated Circuits Conference, pp. 1-5, 2015.
[9] C. Fenouillet-Beranger et al., “New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI”, IEEE International Electron Devices Meeting, pp. 27.5.1-27.5.4, 2015.
[10] D. A. Neamen, “Semiconductor physics and devices: basic principles (fourth edition)”, Mc Graw Hill, 2012.
[11] C. Y. Chang and Y. K. Fang, “Specific contact resistance of metal-semiconductor barriers”, Solid-State Electronics, Vol. 14, pp.541-550, 1971.
[12] K. Barmak and K. Coffey, “Metallic films for electronic, optical and magnetic application”, Woodhead Publishing, pp. 656, 2014.
[13] H. A. Elgomati et al., “Cobalt silicide and titanium silicide effects on nano devices”, IEEE Regional Symposium on Micro and Nano Electronics, pp. 28-30, 2011.
[14] C. M. Osburn et al., “Metal Silicides: Active Elements of ULSI Contacts”, Journals of Electronic Materials, Vol. 25, pp. 1725-1739, 1996.
[15] K. V. Rao et al., “NMOS contact engineering for CMOS scaling”, 15th International Workshop on Junction Technology, pp. 11-12, 2016.
[16] S.-L. Zhang, and M. Östling, “Metal Silicides in CMOS Technology: Past, Present, and Future Trends”, Solid State and Materials Sciences, Vol. 28, pp. 111-129, 2003.
[17] T. Mochizuki et al., “Film properties of MoSi2 and their application to self-aligned MoSi2 gate MOSFET”, IEEE Transactions on Electron Devices, pp. 1431-1435, 1980.
[18] M. Y. Tsai et al., “Properties of WSi2 films on poly-Si”, Journal of Apply Physics, Vol. 52, pp. 5350, 1981.
[19] A. K. Sinha et al., “MOS compatibility of high conductivity TaSi2/N+ poly-Si gates”, IEEE Transactions on Electron Devices, Vol. 27, pp. 1425-1430, 1980.
[20] D. B. Scott et al., “Titanium disilicide contact resistivity and its impact on 1-µm CMOS circuit performance”, IEEE Electron Devices Society, Vol. 34, pp. 562-574, 1987.
[21] J. B. Lasky et al., “Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2”, IEEE Electron Devices Society, 38, p.262-p.269 (1991)
[22] K. Wieczorek et al., “Integration Challenges for Advanced Salicide Processes And Their Impact On CMOS Device Performance”, Materials Research Society, pp. 611, 2000.
[23] K. Ohuchi et al., “Source/Drain Engineering for Sub 100-nm Technology Node”, International Conference on Ion Implantation Technology, pp. 22-27, 2002.
[24] S. K. Sadrnezhaad et al., “Property change during nanosecond pulse laser annealing of amorphous NiTi thin film”, Indian Academy of Sciences, Vol. 35, pp. 357-364, 2012.
[25] S. Gaudet et al., “Thin film reaction of transition metals with germanium”, American Vacuum Society, Vol. 24, pp. 474, 2006.
[26] O. C.-Pluchery et al., “Investigations of transient phase formation in Ti/Si thin film reaction”, American Vacuum Society, Vol. 96, pp. 361, 2004.