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研究生：	蘇品岱 Sue, Pin-dai
論文名稱：	全差動放大器的自動佈局軟體 An Automatic Layout Tool for Fully Differential OPAMPs
指導教授：	張順志 Chang, Soon-jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	88
中文關鍵詞：	全差動運算放大器、佈局、匹配
外文關鍵詞：	Tcl/Tk, layout, laker, GDSII, fully differential opamp
相關次數：	點閱：108 下載：10
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在這篇論文中，我們發展了一個全差動運算放大器的自動佈局軟體，這個軟體可以根據電路進行合成之後的結果來自動產生電路佈局。目前這個軟體支援了三種運算放大器的電路架構：兩級式放大器、摺疊式疊接放大器與兩級式疊接放大器。我們考量了類比電路的特性，在電路進行自動佈局的過程中，會適當地加入佈局匹配、假佈局以及防護圈等技巧，以減少佈局發生電路效能變異的機會。本佈局軟體所產生的佈局檔是Tcl/Tk的指令稿，使用者只要在Laker钓套裝軟體中將這個指令稿讀入，即可自動產生真正的電路佈局。我們的自動佈局軟體目前可應用在台積電0.18贡m 1P6M的製程，產生電路佈局的過程可在1分鐘內完成，而且佈局結果可以通過DRC與LVS的驗證。

In this thesis, we developed an automatic layout tool for fully differential OPAMPs. The tool generates circuit layouts of OPAMPs according to their transistor-level synthesis results. Three OPAMP topologies which include two-stage, folded-cascode and two-stage cascode, are supported by the developed tool. To reduce performance variations caused by layout, some layout schemes, such as matching, dummy and guard ring, are utilized during the procedure of automatic layout. The format of the generated layout is a Tcl/Tk script file which can be sourced into Laker钓 to generate the whole graphic layout. The tool is available for TSMC 0.18贡m 1P6M process. The executing time of automatic layout is within 1 minute. All the automatically generated layouts have been successfully verified by DRC and LVS checks.

List of Figures ..................................................................................................................... iv
List of Tables ...................................................................................................................... vii
Chapter 1 Introduction ....................................................................................................... 1
1.1 Motivation ............................................................................................................... 1
1.2 Thesis Organization................................................................................................. 3
Chapter 2 Analog Layout ................................................................................................... 4
2.1 Points of Layout ...................................................................................................... 4
2.2 Etching and Dummy................................................................................................ 5
2.3 Ratio and Matching ................................................................................................. 6
2.3.1 Common-Centroid Layout ........................................................................... 9
2.3.2 MOS Matching........................................................................................... 15
2.3.3 Capacitance Matching ................................................................................ 27
Chapter 3 Automated Layout for OPAMPs.................................................................... 31
3.1 GDSII .................................................................................................................... 31
3.2 Tcl / Tk .................................................................................................................. 42
Chapter 4 Layout Implement of OPAMPs...................................................................... 58
4.1 Two-Stage OPAMPs.............................................................................................. 58
4.2 Folded-Cascode OPAMPs..................................................................................... 66
4.3 Two-Stage Cascode OPAMPs ............................................................................... 73
4.4 Simulation Results................................................................................................. 83
Chapter 5 Conclusions ...................................................................................................... 86
5.1 Summary ............................................................................................................... 86
5.2 Future Works ......................................................................................................... 87
References .......................................................................................................................... 88
                                    

[1] Chun-Chen Hsu, “CMOS analog circuit layout design automation,” Master thesis, National Cheng-Kung University, Taiwan, Jun. 2003.
[2] A. Hastings, The Art of Analog Layout, Prentice Hall, 2001.
[3] J. F. Gibbons, “Ion Implantation in Semiconductors-Part I: Range Distribution Theory and Experiment,” Proc. IEEE, Vol. 56, #3, 1968, pp. 296-319
[4] F. K. Baker and J. R. Pfiester, “Thn Influence of Tilted Source-Drain Implants on High-Field Effects in Sub-micrometer MOSFETs,” IEEE Trans. On Electron Devices, Vol. 35, #12, 1988, pp. 2119-2124.
[5] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technoloty, New York: McGraw-Hill, 1997, p. 233.
[6] Cadence, Design Data Translators Reference, 1995.
[7] J. K. Ousterhout, Tcl and the Tk Toolkit, Addison-Wesley, 1994.
[8] M. Harrison, Tcl/Tk Tools, O'Reilly, 1997.
[9] Cheng-Wu Lin, “An automated synthesis tool for fully differential OPAMPs,” Master thesis, National Cheng-Kung University, Taiwan, Jul. 2006.
[10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

校內：2009-08-27公開
校外：2011-08-27公開

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