| 研究生: |
陳泳超 Chen, Yung-Chao |
|---|---|
| 論文名稱: |
可延展型多執行緒爪哇虛擬機器之系統晶片軟硬體協同設計 SoC SW/HW Co-Design of A Scalable Multi-Threaded JVM |
| 指導教授: |
周哲民
Jou, Jer-Min |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 中文 |
| 論文頁數: | 65 |
| 中文關鍵詞: | 系統晶片 、軟硬體協同設計 、爪哇 、可延展 、多執行緒 、虛擬機器 |
| 外文關鍵詞: | Scalable, Multi-Threaded, JVM, SW/HW Co-Design, SoC |
| 相關次數: | 點閱:102 下載:3 |
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Java語言的成功已漸漸受到了重視,透過Java虛擬機器的技術,使得Java具有跨平台的特性,消除了程式移植於不同平台所耗費的時間、人力,大大縮短設計週期,且Java本身更融入的多執行緒功能,提高了程式的執行效率;然而Java虛擬機器本身執行效率不佳,許多加速執行的方法紛紛被提出,例如軟體即時編譯器(JIT Complier),或是直接以硬體實現Java虛擬機器,將多數的軟體機制都交付硬體處理,達到真正的高效能。
本論文將以軟硬體共同設計的方式,實作出一個支援多執行緒之Java虛擬機器,Java執行緒程式,可經由一般的編譯器產生,並透過特製的類別載入者載入執行;系統架構上由兩組中央控制器(執行緒管理者、記憶體管理者)與多組的處理單元所組成,硬體可自動發派執行緒到各處理單元上,以平行處理方式執行多執行緒,而不需透過軟體或作業系統的輔助;此外,執行緒機制由軟體端轉移至硬體層級,其執行緒的狀態轉移,多數可在2個時脈內完成,達到了高效能。最後系統的驗證以撰寫VHDL的方式於FPGA平台上驗證(Altrea Stratix II Family),系統時脈在處理單元數目小於7時,可達到96.8MHz且由實驗結果得知本架構無論在面積或效能方面均具有延展性(Scalability),使用者可經由模擬,彈性地增加處理單元的數量,以達到成本與效能間的平衡。
In this paper, we have designed and implemented a Multi-Threaded Java Virtual Machine (MTJVM) which is composed of multiple processing elements (PEs) and can directly execute Java threads concurrently without any software/OS support. Threads will be dynamically dispatched to PEs and run simultaneously toward Thread-Level-Parallelism (TLP). The thread processing mechanisms and instructions, such as real-time scheduling, sleep, wait, yield, and synchronization, are handled by two new global controllers, the thread-manager and the memory-manager. The complete system has been coded and synthesized in C and VHDL for its software and hardware parts, respectively. As the experiment results shown, the performance and the area of it are scalable with the number of PEs used, and it works at 96.8 MHz.
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