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研究生: 陳泳超
Chen, Yung-Chao
論文名稱: 可延展型多執行緒爪哇虛擬機器之系統晶片軟硬體協同設計
SoC SW/HW Co-Design of A Scalable Multi-Threaded JVM
指導教授: 周哲民
Jou, Jer-Min
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 65
中文關鍵詞: 系統晶片軟硬體協同設計爪哇可延展多執行緒虛擬機器
外文關鍵詞: Scalable, Multi-Threaded, JVM, SW/HW Co-Design, SoC
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  • Java語言的成功已漸漸受到了重視,透過Java虛擬機器的技術,使得Java具有跨平台的特性,消除了程式移植於不同平台所耗費的時間、人力,大大縮短設計週期,且Java本身更融入的多執行緒功能,提高了程式的執行效率;然而Java虛擬機器本身執行效率不佳,許多加速執行的方法紛紛被提出,例如軟體即時編譯器(JIT Complier),或是直接以硬體實現Java虛擬機器,將多數的軟體機制都交付硬體處理,達到真正的高效能。
    本論文將以軟硬體共同設計的方式,實作出一個支援多執行緒之Java虛擬機器,Java執行緒程式,可經由一般的編譯器產生,並透過特製的類別載入者載入執行;系統架構上由兩組中央控制器(執行緒管理者、記憶體管理者)與多組的處理單元所組成,硬體可自動發派執行緒到各處理單元上,以平行處理方式執行多執行緒,而不需透過軟體或作業系統的輔助;此外,執行緒機制由軟體端轉移至硬體層級,其執行緒的狀態轉移,多數可在2個時脈內完成,達到了高效能。最後系統的驗證以撰寫VHDL的方式於FPGA平台上驗證(Altrea Stratix II Family),系統時脈在處理單元數目小於7時,可達到96.8MHz且由實驗結果得知本架構無論在面積或效能方面均具有延展性(Scalability),使用者可經由模擬,彈性地增加處理單元的數量,以達到成本與效能間的平衡。

    In this paper, we have designed and implemented a Multi-Threaded Java Virtual Machine (MTJVM) which is composed of multiple processing elements (PEs) and can directly execute Java threads concurrently without any software/OS support. Threads will be dynamically dispatched to PEs and run simultaneously toward Thread-Level-Parallelism (TLP). The thread processing mechanisms and instructions, such as real-time scheduling, sleep, wait, yield, and synchronization, are handled by two new global controllers, the thread-manager and the memory-manager. The complete system has been coded and synthesized in C and VHDL for its software and hardware parts, respectively. As the experiment results shown, the performance and the area of it are scalable with the number of PEs used, and it works at 96.8 MHz.

    摘要...................................I Abstract...............................II 第一章 緒論............................1 1.1 研究背景與動機.....................1 1.2 研究目的...........................1 1.3 論文架構...........................2 第二章 背景與相關研究..................3 2.1 Java架構...........................4 2.2 虛擬機器...........................4 2.2.1 虛擬機器簡介.....................4 2.2.2 虛擬機器語言.....................5 2.2.3 虛擬機器缺點.....................5 2.3 Java處理器.........................6 2.3.1 設計空間分析.....................6 2.3.1.1 一般性分析.....................6 2.3.1.2 Bytecode處理之相容度...........8 2.3.1.3 高複雜度之Bytecode處理.........8 2.3.2 執行引擎探討.....................9 2.3.3 並行度探討......................10 2.3.3.1 指令並行度....................10 2.3.3.2 執行緒並行度..................11 第三章 系統架構軟硬體共同設計.........15 3.1 系統架構..........................15 3.1.1 設計目標........................15 3.1.2 設計複雜度探討..................17 3.2 軟體設計..........................17 3.2.1 類別載入者......................17 3.2.2 多執行緒程式....................19 3.3 硬體架構..........................21 3.3.1 指令集..........................21 3.3.2 基本處理單元....................23 3.3.2.1 指令擷取級....................23 3.3.2.2 指令解碼級....................24 3.3.2.3 運算元擷取級..................24 3.3.2.4 執行運算級....................26 3.3.2.5 記憶體存取級..................26 3.3.2.6 寫回..........................27 3.3.3 執行緒管理者....................28 第四章 多執行緒並行處理設計...........29 4.1 Java多執行緒......................31 4.2 執行緒管理........................31 4.2.1 執行緒控制單元..................32 4.2.2 仲裁器設計......................33 4.2.2.1 Wait/Sleep Set仲裁器..........33 4.2.2.2 Ready Set仲裁器...............33 4.2.2.3 Synchronization Set仲裁器.....34 4.3 執行緒狀態實作....................35 4.3.1 執行緒環境......................35 4.3.2 產生執行緒......................37 4.3.2.1 多執行緒程式撰寫..............37 4.3.2.2 執行緒的初始化................37 4.3.2.3 執行緒的生成..................38 4.3.3執行執行緒.......................38 4.3.3.1 執行緒準備....................38 4.3.3.2 執行緒執行....................40 4.3.3.3 環境切換機制..................40 4.3.4 凍結執行緒......................42 4.3.4.1 執行緒的睡眠..................42 4.3.4.2 執行緒的等待..................44 4.3.4.3 執行緒的同步..................45 4.3.5 結束執行緒......................47 第五章 實驗結果與數據分析.............48 5.1 模擬流程與環境....................48 5.2 實驗結果..........................48 5.2.1 硬體面積與效能探討..............49 5.2.2 執行緒狀態轉移效能評估..........51 5.2.3 多執行緒效能測試................52 5.3 硬體限制..........................55 第六章 結論與未來展望.................57 參考文獻..............................58 附錄..................................60 (一)[FIR.Java]......................60 (二)最佳化之操作碼..................62 (三)執行緒指令使用說明..............63 (四)多執行緒範例程式................65

    [01] Chun-Mok Chung and Shin-Dug Kim, “A Dualthreaded Java Processor for Java Multithreading”, Parallel and Distributed Systems, 1998. Proceedings., 1998 International Conference on Publication Date: 14-16 Dec 1998
    [02] HARIPRAKASH G., R. ACHUTHARAMAN, AMOS R. OMONDI, “Hardware compilation for high performance Java processors”
    [03] Frank Golatowski, Hagen Ploog, Nico Bannow and Dirk Timmermann, “A small Java processor core for smart cards and embedded system”, International Conference on Architecture of Computing Systems -Trends in Network and Pervasive Computing - Java in Embedded Systems - ARCS 2002, ISSN: 3-8007-2686-6, S. 135-140, Karlsruhe, April 2002
    [04] Michael O'Connor J., Marc Tremblay, "PicoJava-I: The Java Virtual Machine in Hardware," IEEE Micro, vol. 17, no. 2, pp. 45-53, Mar/Apr, 1997
    [05] Jochen Kreuzinger, Theo Ungerer, "Context-Switching Techniques for Decoupled Multithreaded Processors," euromicro, p. 1248, 25th Euromicro Conference (EUROMICRO '99)-Volume 1, 1999
    [06] Zhi-gang Mao, Wang Tao, Ye Yi-zheng, “Designing JCVM In hardware”
    [07] Jon Meyer, Troy Downing, “Java Virtual Machine”, O’Reilly Publish 2000.
    [08] Pfeffer M., S. Uhrig, Th. Ungerer, U. Brinkschulte, “A Real-Time Java System on a Multithreaded Java Microcontroller”, Object-Oriented Real-Time Distributed Computing, 2002. (ISORC 2002). Proceedings. Fifth IEEE International Symposium on Publication Date: 2002 On page(s): 34-41
    [09] Watheq, M.et.al., “A design space analysis of Java processors”, Proce. of IEEE Communications, Computers and signal Pacific Rim Conference, 2003.
    [10] Schoeberl M., JOP: A Java Optimized Processor for Embedded Real-Time Systems, PhD thesis, Vienna University of Technology, 2005.
    [11] Watcharawitch P., S. Moore, “MulTEP: MultiThreaded Embedded Processors”, International Symposium on Low-Power and High-Speed Chips IV, vol. I. the IEEE/IEICE/IPSJ /ACM SIGARCH, 2003.
    [12] Naohiko Shimizut, Makoto Naitot, “A Dual Issue Queued Pipelined Java Processor TRAJA”, ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on On page(s): 213-216,1999
    [13] Shondip Sen, Henk Muller, David May, “Synchronisation in a Multithreaded Processor”, Communicating Process Architectures 2000
    [14] Oyvind Strom and Einar J. Aas, “A Novel Microprocessor Architecture for Executing Byte Compiled Java Code”, Proceedings ofthe International Conference on Chip Design, 2000
    [15] David S. Hardin, "Real-Time Objects on the Bare Metal: An Efficient Hardware Realization of the JavaTM Virtual Machine," isorc, p. 0053, Fourth International Symposium on Object-Oriented Real-Time Distributed Computing, 2001
    [16] Marius Stoian, Gheorghe Stefan, “A multithreading architecture for low power processor”, Semiconductor Conference, 2005. CAS 2005 Proceedings. 2005 International Publication Date: 3-5 Oct. 2005 Volume: 2, on page(s): 387- 390 vol. 2
    [17] Alpha Assembly Language Guide
    [18] Java 2 Platform Standard Edition 5.0 API Specification, http://java.sun.com, 2006.
    [19] The Java Virtual Machine Specification, http://java.sun.com/docs/books/jvms/

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