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研究生：	簡君珉 Jian, Jun-Min
論文名稱：	具低輸出電壓漣波之高降壓直流-直流轉換器研製 High Step-Down DC-DC Converter with Low Output Voltage Ripple
指導教授：	陳建富 Chen, Jiann-Fuh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2019
畢業學年度：	107
語文別：	英文
論文頁數：	60
中文關鍵詞：	高降壓比、低輸出電壓漣波、負載點轉換器
外文關鍵詞：	High step-down ratio, Low output voltage ripple, Point-of-load converter
相關次數：	點閱：89 下載：5
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隨著科技的進步，人們的一舉一動都被儲存於雲中，成為大數據中的一部分，而儲存大數據的數據中心每年所消耗的電力已達全球耗電量的百分之3，莫約400太瓦小時，高於英國每年約300太瓦小時的耗電量。Google提出新含有負載點轉換之電源架構，目的在於減少數據中心之龐大耗損。傳統轉換鏈將48伏特轉至負載點電壓後，必須透過兩級轉換。而新架構中僅需一級轉換及可得到負載點電壓。對此，本文提出此一級轉換之轉換器-具低輸出漣波之高降壓直流-直流轉換器，透過結合交錯式轉換器之概念，達到降低輸出電流及電壓漣波，可應用於如具高性能中央處理器及圖形處理器系統之電源供應器。於本文中，轉換器動作原理分析及參數設計皆會加以討論，並且透過軟體SIMPLIS®模擬其可行性。
最後，根據本文所提出之拓樸，研製一規格為48 伏特輸入電壓、3.3 伏特輸出電壓及20 安培額定電流之電路，對本文所提出之拓樸進行實現及驗證。

With the advancement of technology, people's behavior is stored in the cloud, which is becoming a part of information in big data. The place where the big data stored has consumed 3 % of the world's electricity consumption every year, about 400 terawatts hours, which is higher than the electricity consumption of about 300 terawatts hours per year in the United Kingdom. Google proposes a new power architecture with 48 V to point-of-load design to reduce the huge consumption from data center. After transferring to POL voltage from 48 volt, the two stage conversion are required for conventional converter chain, but only single stage conversion for new architecture proposed by Google. Therefore, based on single stage conversion, a high step-down DC-DC converter with low output ripple is proposed in this thesis. The two coupled inductors are applied to realize the concept of interleave converter, and the ripple of output current and output voltage are reduced. This converter is suitable for systems with high performance GPUs and CPUs. The operating principle and parameter design of the proposed converter are discussed and simulated by the software SIMPLIS®.
Finally, according to the topology proposed in this thesis, a circuit with a specification of 48 V input voltage, 3.3 V output voltage and 20 A rated current is implemented to verify the feasibility of proposed topology in this thesis.

摘要  I
Abstract  II
Acknowledgement  III
Content  IV
List of Table  VI
List of Figure  VII
CHAPTER 1 INTRODUCTION  1
1.1 Background and Motivation  1
1.2 Thesis Outline  4
CHAPTER 2 REVIEW OF TOPOLOGIES  5
2.1 Isolated Converter  5
2.2 Non-isolated Converter  9
2.2.1 Buck Converter  9
2.2.2 Tapped-inductor Buck Converter  10
2.2.3 Tapped-Inductor (TI) Buck Converter with Active Clamp Circuit  11
2.2.4 TI Buck Converter with a Series Clamping Capacitor Circuit  12
2.2.5 Tapped-Inductor with Impedance-source Cell  13
CHAPTER 3 ANALYSIS OF PROPOSED CONVERTER  16
3.1 The Proposed Converter  16
3.2 Operating Principle  19
3.3 Steady State Analysis  27
3.3.1 Derivation of Voltage Conversion Ratio  28
3.3.2 Design Considerations of the Coupled Inductors  30
CHAPTER 4 PARAMETERS DESIGN AND SIMULATION  34
4.1 Parameters Design of Components  34
4.1.1 Duty cycle  34
4.1.2 The magnetizing Inductors Lm1 and Lm2  35
4.1.3 The Capacitor C1 and Capacitor C2  38
4.1.4 The Output Capacitor Co  40
4.1.5 The Switches S1, S2, S3, S4 and S5  40
4.2 Simulation  41
4.3 The Gate Drive  45
CHAPTER 5 EXPERIMENTAL RESULTS AND DISCUSSIONS  47
5.1 Experimental Waveforms  47
5.2 Efficiency  55
CHAPTER 6 CONCLUSIONS AND FUTURE WORKS  56
6.1 Conclusions  56
6.2 Future Works  57
REFERENCES  58
                                    

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校內：2024-01-22公開
校外：2024-01-22公開

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