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研究生： 徐毓昕
Syu, Yu-Sin
論文名稱： 使用頻率偵測器之寬頻鎖定雙迴路類比式延遲鎖定迴路
A Dual-Loop Wide-Range Analog Delay Lock Loop with a Frequency Detector
指導教授： 劉濱達
Liu, Bin-Da
魏嘉玲
Wei, Chia-Ling
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 81
中文關鍵詞： 延遲鎖定迴路 、雙迴路 、寬頻
外文關鍵詞： Delay lock loop, dual loop,, wide range
相關次數： 點閱：87  下載：6 
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    • 本論文提出一個應用在寬頻操作頻率的延遲鎖定迴路，具有良好的抖動性能。本架構使用頻率偵測器來自動選擇電荷幫浦的電流值，並改善電壓控制延遲線的非線性現象，以保持抖動性能和鎖定時間。此系統使用雙迴路架構，其細調迴路目的使相位偵測器的死帶縮小，以提升抖動效能。
    此延遲鎖定迴路採用聯華電子公司0.18 um一層多晶矽六層金屬導線互補式金屬氧化物半導體製程實現，晶片面積為0.14 mm2。由佈局模擬結果顯示，可操作之頻率範圍為20 MHz至1 GHz。在電源電壓為 1.8 V和操作頻率為1 GHz的量測條件下，峰對峰值抖動為23 ps，功率消耗為20.9 mW。

    This thesis proposes a delay lock loop that operates over a wide frequency range and exhibits good jitter performance. The adopted frequency detector determines the current for the charge pump, which can improve the nonlinear delay gain of the voltage-controlled delay line to maintain the jitter performance and the locking time. Besides, a dual loop is applied in the system to minimize the dead zone of the phase detector, increasing the jitter performance.
    The proposed DLL has been fabricated by UMC 0.18-µm 1P6M CMOS technology, and the core area of the chip is 0.14 mm2. Simulation results show that the proposed DLL can achieve the frequency range from 20 MHz to 1 GHz at 1.8 V supply voltage. When the operation frequency is 1 GHz, the peak-to-peak jitter is 21 ps and the power consumption is 20.9 mW.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Figures ix List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Overview of DLL 3 2.1 Basic Concept of DLL 3 2.1.1 Phase Lock Loop 3 2.1.2 Conventional Analog DLL 4 2.2 Relative Paper of DLL 7 2.2.1 Replica Delay Line 7 2.2.2 Dual Loop 10 2.2.3 Scaling Circuit 12 Chapter 3 Architecture of the Proposed Circuit 14 3.1 The Proposed Architecture of the DLL 14 3.2 Start-up Circuit 16 3.3 Phase Detector 18 3.4 Charge Pump 20 3.5 Voltage-Controlled Delay Line 25 3.6 Frequency Detector 29 3.7 Time Amplifier 31 3.8 Lock Detector 36 Chapter 4 Simulation and Experimental Results 38 4.1 Layout and Simulation Results 38 4.1.1 Layout 38 4.1.2 Simulation Results 41 4.1.3 PVT Variations 48 4.2 Measurement Results and Discussion 63 4.2.1 Measurement Results 63 4.2.2 Discussion 72 4.3 Comparison 74 Chapter 5 Conclusion 75 5.1 Conclusion 75 5.2 Future Work 76 References………………………………………………………………………...............77 Biography………………………………………………………………………...............81

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