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研究生： 侯智輝
Hou, Chih-Huei
論文名稱： 一個使用只有前置放大器的比較器以及不需校正機制之八位元每秒取樣四億次的逐漸趨近式類比數位轉換器
An 8-bit 400-MS/s Calibration-Free SAR ADC with a Pre-amplifier-only Comparator
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2016
畢業學年度： 105
語文別： 英文
論文頁數： 136
中文關鍵詞： 逐漸趨近式類比數位轉換器 、非二進位演算法 、多組比較器 、不需校正只有前置放大器的比較器 、高增益的動態前置放大器
外文關鍵詞： Successive approximation register (SAR) analog-to-digital converter (ADC), redundancy (or non-binary) algorithm, multiple comparators, calibration-free, pre-amplifier-only comparator, high-gain dynamic pre-amplifier
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    • 本論文呈現一個使用90奈米製程的單通道八位元每秒取樣四億次的逐漸趨近式類比數位轉換器。
    我們針對應用於高速且不需複雜校正機制的逐漸趨近式類比數位轉換器，提出了一個混合的架構。在前面粗解析的位元循環裡，我們採用可提升速度的迴圈展開式的技巧，並用非二進位的搜尋演算法來容忍前後位元循環間的不匹配，以維持整體性能；針對後面細解析的位元循環，我們提出兩個電路技巧來增快速度：首先，我們提出一個只使用前置放大器作為比較器的設計，其可以減少等待比較器重置的時間；再來，我們提出一個具有高增益的動態前置放大器來減輕栓鎖器間的不匹配(mismatch)效應以達到整體精確度要求。藉由上述所提的技巧，我們的作品不需任何的校正機制。
    本設計以台積電90奈米CMOS標準1P9M製程實作晶片，其核心電路面積佔了0.0276 mm2。量測結果顯示，在1.2伏特電源供應及每秒四億次的取樣頻率下，消耗功率為3.198 mW；在沒有使用複雜的校正電路下，最高的有效位元為7.15位元，每次的資料轉換所消耗的能量為56.29 fJ。

    A single-channel 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) in 90-nm CMOS process is presented in this thesis.
    We propose a hybrid architecture for high-speed SAR ADC without a complex calibration engine. The operation speed is enhanced by adopting the loop-unrolled technique in the coarse conversions. Considering the mismatch between coarse and fine conversions, we adopt the non-binary search scheme with redundancy to maintain the overall performance. Moreover, two circuit techniques are proposed to increase the operation speed in the fine conversions. Firstly, a pre-amplifier-only comparator is proposed to shorten the critical timing path in the fine conversions. It significantly reduces the comparator reset time. Secondly, we propose a high-gain dynamic pre-amplifier to mitigate the offset mismatches among the latches for the requirement of the overall accuracy. With the above-mentioned techniques, it leads to a calibration-free design.
    The proof-of-concept prototype was fabricated in a TSMC 90-nm CMOS technology. The core area occupies 0.0276 mm2. At a supply voltage of 1.2-V and sampling rate of 400-MS/s, the power consumption of the SAR ADC is 3.198 mW. The peak ENOB is 7.15 bits without complex calibration circuit. It achieves a figure of merit (FoM) of 56.29 fJ/conversion-step.

    摘　要 III Abstract V List of Tables X List of Figures XI List of Abbreviations XVI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 5 Chapter 2 Design Considerations for High-speed SAR ADCs 6 2.1 Basics of SAR ADCs 7 2.2 Speed Limitations for SAR ADCs 9 2.2.1 Comparison Time 10 2.2.2 DAC Settling Time and Comparator Resetting Time 15 2.2.3 Digital Circuit Gate Delay 19 2.3 Redundancy Algorithm in SAR ADCs 21 2.3.1 Overview 21 2.3.2 Types of Non-binary SAR ADCs 31 2.3.3 Application 33 Chapter 3 Design Techniques for High-speed SAR ADCs 38 3.1 Introduction 38 3.2 Timing Processing 39 3.3 Simplified Digital Control Circuits 42 3.4 Sub-ranging Architectures 48 3.5 Multi-comparator Architectures 61 3.6 Summary 67 Chapter 4 An 8-bit 400-MS/s SAR ADC 69 4.1 Introduction 69 4.2 Architecture Consideration 70 4.2.1 Hybrid Coarse Fine SAR ADC Architecture 70 4.2.2 Redundancy Algorithm Design Consideration 73 4.2.3 Capacitor Switching Method 75 4.3 Proposed Techniques 81 4.3.1 Timing Control Scheme with a Pre-amp-only Comparator 81 4.3.2 Dynamic High-gain Pre-amplifier 86 4.4 Architecture of the Proposed SAR ADC 91 4.5 Key Circuit Building Blocks 94 4.5.1 Bootstrapped Switch 94 4.5.2 Dynamic Comparators 98 4.5.3 Digital Control Logic Circuits 101 4.5.4 Capacitive DAC 106 Chapter 5 Simulation and Measurement Results 108 5.1 Layout and Chip Floor Plan 108 5.2 Simulation Results 111 5.3 Die Micrograph and Measurement Setup 116 5.4 Measurement Results 119 Chapter 6 Conclusions and Future Works 126 Bibliography 129

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