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研究生： 陳育萱
Chen, Yu-Hsuan
論文名稱： 利用對稱性濾波器之可重組資料路徑設計用於人工智慧晶片之硬體加速器
Hardware Accelerator for AI on Chip via Reconfigurable Data Path Design for Symmetrical Filters
指導教授： 李國君
Lee, Gwo-Giun
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 70
中文關鍵詞： 可重組 、資料流模型 、硬體實現 、賈伯濾波器
外文關鍵詞： Reconfigurable, Dataflow Model, Hardware Implementation, Gabor Filter
相關次數： 點閱：102  下載：0 
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    • 本論文實現用於計算轉換濾波器之硬體。我們使用特徵轉換法將賈伯濾波器轉換為轉換濾波器，基於轉換濾波器之對稱性，將乘上相同參數的輸入資料預先加總，以達到減少乘法運算之效果。我們根據數學式建立四種資料流模型作為硬體實現的雛型架構，並利用四種資料流模型之共同處實現對硬體架構的最佳化，為增加硬體可共用處，將部分模型之功能進行整合為一可重組模型，以此減少架構實現的面積成本。最後，根據演算法暨架構共同探索之四個指標，分析各架構之間的優劣。

    This paper implements a hardware that computes the transformed filters. We use Eigen-transformation approach to convert Gabor filters into transformed filters, we pre-add the input data which multiply the same coefficients to reduce the number of multiplications. According to the formula, we build four types of dataflow models as prototypes to implement hardware and utilize the commonality of four dataflow models to optimize the architecture, we integrate the functions of part model as a reconfigurable model to increase the common part of hardware and reduce the budget of cell area. Finally, we analyze the advantages and disadvantages between these architectures according to four indexes in algorithm architecture co-design.

    摘 要 i Abstract ii 誌 謝 iv Table of Contents vi List of Tables ix List of Figures x Chapter 1 Introduction 1 1.1 Objective 1 1.2 Motivation 1 1.3 Background Information 2 1.3.1 Machine Learning 3 1.3.1.1 Deep Learning 3 1.3.1.2 Convolution Neural Network (CNN) 4 1.3.2 Algorithm/Architecture Co-design (AAC) 7 1.3.3 Related Work 9 1.3.3.1 Google TPU 9 1.3.3.2 Eyeriss 10 1.3.4 Reconfigurability 11 1.4 Contributions of this Thesis 11 Chapter 2 Applied Methods 13 2.1 Gabor Filter 14 2.2 Eigen-Transformation Approach 15 2.3 Low Rank Approximation to Eigen-Transformation 22 Chapter 3 Architecture Design 25 3.1 Pre-add 25 3.2 Pre-add in Symmetrical Properties 26 3.3 Transformed Filters in Four Patterns 28 3.3.1 Dataflow 28 3.3.2 Sub-modules 30 3.3.2.1 Even Point Symmetry 30 3.3.2.2 Vertical Symmetry 31 3.3.2.3 Diagonal Symmetry 32 3.3.3 Commonality in Four Patterns 33 3.3.4 Architecture with Commonality 33 3.3.5 Reconfigurable of Even and Odd Module 34 3.3.6 Pipeline Design 35 3.4 Feeder Model 35 3.5 Complexity Analysis of Implementation 37 3.5.1 Number of Operations 38 3.5.2 Degree of Parallelism 38 3.5.3 Data Transfer 38 3.5.4 Data Storage 39 Chapter 4 Experimental Results 40 4.1 Filter Model Implementation 41 4.1.1 Original Model of Four Patterns 41 4.1.1.1 Accuracy of Transformed Filter 42 4.1.1.2 Dataflow Model 43 4.1.1.3 Implementation Results 47 4.1.1.4 Number of Operations 47 4.1.1.5 Degree of Parallelism 48 4.1.1.6 Data Transfer 48 4.1.1.7 Data Storage 48 4.1.2 Model via Commonality 49 4.1.2.1 Sharing Input Buffer 50 4.1.2.2 Sharing Even Point Symmetry 51 4.1.2.3 Commonality Model 52 4.1.2.4 Dataflow Model 52 4.1.2.5 Implementation Results 54 4.1.2.6 Number of Operations 54 4.1.2.7 Degree of Parallelism 54 4.1.2.8 Data Transfer 55 4.1.2.9 Data Storage 55 4.1.3 Architecture via Reconfigurable of Even/Odd Model 56 4.1.3.1 Dataflow Model 57 4.1.3.2 Implementation Results 58 4.1.3.3 Number of Operations 58 4.1.3.4 Degree of Parallelism 58 4.1.3.5 Data Transfer 59 4.1.3.6 Data Storage 59 4.1.4 Reference Architecture 60 4.1.4.1 Dataflow Model 61 4.1.4.2 Implementation Results 62 4.1.4.3 Number of Operations 62 4.1.4.4 Degree of Parallelism 62 4.1.4.5 Data Transfer 62 4.1.4.6 Data Storage 63 4.1.5 Pipeline Design 63 4.2 Architecture Comparison 63 Chapter 5 Conclusion and Future Work 65 5.1 Conclusion 65 5.2 Future Work 66 References 67

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