| 研究生: |
呂良盈 Lu, Liang-Ying |
|---|---|
| 論文名稱: |
三維積體電路多處理器系統之熱分析 Thermal Analysis for Multiprocessor Systems of Three-Dimensional Integrated Circuits |
| 指導教授: |
邱瀝毅
Chiou, Lih-Yih |
| 學位類別: |
博士 Doctor |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2018 |
| 畢業學年度: | 106 |
| 語文別: | 英文 |
| 論文頁數: | 119 |
| 中文關鍵詞: | 三維積體電路 、多處理器系統 、熱分析 、熱分析加速 、虛擬平台 、電子系統層級 |
| 外文關鍵詞: | Three-dimensional integrated circuits (3D ICs), multiprocessor system, thermal analysis, the acceleration of thermal analysis, virtual platform, electronic system level (ESL) |
| 相關次數: | 點閱:111 下載:1 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著多處理器系統設計的複雜度增加,三維積體電路將有利於多處理器系統設計。然而,三維積體電路搭配先進製程可能導致嚴重的熱效應。熱效應將對系統的效能、功率消耗、可靠性和冷卻成本造成顯著地影響。至今,網格熱分析是被廣泛地利用去分析熱效應。熱分析的分析效能和準確性是相互影響的。因此,如何在早期系統設計階段,快速和有效地分析熱效應將是一個迫切的問題。
傳統積體電路熱分析方法忽略溫度相依的因素和這熱分析結果無法反映晶片的熱效應在早期系統設計階段。因此,我們考量溫度相依的因素(熱輻射、材質熱導和漏電功率消耗) 在提出的溫度梯度感知熱分析方法裡去較好的顯示出晶片的熱效應在架構層級的積體電路設計階段。
網格熱分析是被廣泛地利用在熱分析方法裡。網格數目是常由使用者去彈性的定義。然而,一個不合適的網格單元數目在網格熱分析中可能降低分析效能和損失準確度。因此,我們提出一個溫度梯度探索方法去決定一個合適的網格單元數目,並且使用在網格熱分析中以達到高分析效能和準確度。
網格熱分析需要使用大數量的熱傳導公式在一個矩陣運算的形式裡。為了提高網格熱分析效能,矩陣運算仍然可以藉由圖形處理器再加速。然後,我們提出一個新的矩陣壓縮的方法去加速此熱分析方法的網格熱分析平均12.48倍。
系統設計者需要一個電子系統層級具功率和熱感知的虛擬平台去分析系統的熱效應由於較短系統設計時間和較低系統設計成本的好處。傳統的功率感知虛擬平台不具備熱感知。因此,我們提出一個方法論關於功率感知的虛擬平台發展至功率和熱感知的虛擬平台。此方法論讓傳統的電子系統層級功率感知虛擬平台能有系統地具備熱的分析能力。
總結,此提出的方法之研究能輔助系統設計者設計出高可靠性、高效能及低功耗之三維積體電路多處理器系統。
With the design complexity growth of multiprocessor systems, three-dimensional integrated circuit (3D IC) will benefit the design of multiprocessor systems. However, 3D-IC with advanced process techniques may incur serious thermal effects. The thermal effects will significantly affect the performance, power consumption, reliability, and cooling cost of the system. To date, mesh-based thermal analysis is commonly utilized to analyze the thermal effects. The analytical performance and accuracy of the thermal analysis are affected by each other. Therefore, how to fast and effectively analyze the thermal effects of ICs at early stages of system design is an urgent problem.
Conventional thermal analysis methods of ICs ignore temperature-dependent factors, and the results of the thermal analysis cannot reflect the thermal effects of ICs at early stages of system design. Therefore, we consider the temperature-dependent factors (specifically thermal radiation, the thermal conductivity of materials, and leakage power consumption) in the proposed temperature gradient-aware thermal analysis (TGA) method to better manifest the thermal effects at the architecture level of design stage.
The mesh-based thermal analysis is often used to observe the variations and distribution of the temperatures in ICs. The number of cells in the mesh is often defined by the users to provide flexibility. However, an unsuitable number of the cells in the mesh-based analysis may reduce analytical performance while losing analytical accuracy. Hence, we propose a temperature gradient exploration method (called TGE) for determining the appropriate number of the cells used in the mesh-based thermal analysis to achieve high analytical performance and accuracy.
The mesh-based thermal analysis needs to solve a large number of heat transfer equations in a form of matrix operations. In order to increase the performance of the mesh-based thermal analysis, the matrix computation can be further accelerated by a graphics processing unit (GPU). Then, we propose a novel matrix compression method to speed up the mesh-based thermal analysis of TGA by 12.48 times on average.
System designers require a power- and thermal-aware virtual platform at electronic system level (ESL) to analyze the thermal effects of systems because of the benefits of shorter time and lower cost in system design. Conventional power-aware virtual platforms are not thermal aware. Therefore, we propose a methodology for developing power-aware virtual platforms to power- and thermal-aware virtual platforms. The methodology let conventional power-aware virtual platforms incorporate with thermal analysis capability systematically.
In summary, the proposed methods can assist system designers to design the multiprocessor systems of 3D ICs with higher reliability, higher performance, and lower power consumption.
[1] Chia-Hong Jan, “10 Years of Transistor Innovations in System-on-Chip (SoC) Era,” in Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology, 2014, pp. 1–4.
[2] Yibo Chen, Dimin Niu, Yuan Xie, and Krishnendu Chakrabarty, “Cost-Effective Integration of Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis,” in Proc. IEEE International Conference on Computer-Aided Design, 2010, pp. 471–476.
[3] Xiangyu Dong and Yuan Xie, “System-Level Cost Analysis and Design Exploration for Three-Dimensional Integrated Circuits (3D ICs),” in Proc. IEEE Asia and South Pacific Design Automation Conference, 2009, pp. 234–241.
[4] Stephen Tarzia, “A Survey of 3D Circuit Integration,” March 14, 2008.
[5] Robert S. Patti, “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1214–1224, June 2006.
[6] Jian-Qiang Lu, “3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems,” Proceedings of the IEEE, vol. 97, no. 1, pp. 18–30, Jan. 2009.
[7] Flynn Carson and Young-Cheol Kim, “The Development of a Novel Stacked Package: Package in Package,” in Proc. IEEE 29th International Electronics Manufacturing Technology Symposium, 2004, pp. 91–96.
[8] Yuan Xie, Jason Cong, and Sachin Sapatnekar, Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. New York: Springer, 2012.
[9] Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, and Erik Jan Marinissen, “Test Cost Analysis for 3D Die-to-Wafer Stacking,” in Proc. IEEE Asian Test Symposium, 2010, pp. 435–441.
[10] W. Rhett Davis, John Wilson, Stephen Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael Steer, and Paul D. Franzon, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498–510, Nov. 2005.
[11] Zhe Li, Yuan Li, and John Xie, “Design and Package Technology Development of Face-to-Face Die Stacking as a Low Cost Alternative for 3D IC Integration,” in Proc. IEEE 64th Electronic Components and Technology Conference, 2014, pp. 338–341.
[12] Robert Sung, Kevin Chiang, Daniel Lee, and Mike Ma, “High-Speed Electrical Design Study for 3D-IC Packaging Technology,” in Proc. International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2011, pp. 144–146.
[13] Yue Zhang, Calvin R. King Jr., Jesal Zaveri, Yoon Jo Kim, Vivek Sahu, Yoenda Joshi, and Muhannad S. Bakir, “Coupled Electrical and Thermal 3D IC Centric Microfluidic Heat Sink Design and Technology,” in Proc. IEEE 61st Electronic Components and Technology Conference, 2011, pp. 2037–2044.
[14] Li Li, Paul Ton, Mohan Nagar, and Pierre Chia, “Reliability Challenges in 2.5D and 3D IC Integration,” in Proc. IEEE 67th Electronic Components and Technology Conference, 2017, pp. 1504–1509.
[15] Assem Gupta, Sudeep Pasricha, Nikil Dutt, Fadi Kurdahi, Kamal Khouri, and Magdy Abadir, “On Chip Communication-Architecture Based Thermal Management for SoCs,” in Proc. International Symposium on VLSI Design, Automation and Test, 2009, pp. 76–79.
[16] Sivasubramaniam Krishnamurthy, Somnath Paul, and Swarup Bhunia, “Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration,” in Proc. International Symposium on Quality Electronic Design, 2007, pp. 755–760.
[17] Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty, and Sandip Kundu, “On Improving Reliability of Delay Based Physically Unclonable Functions under Temperature Variations,” in Proc. IEEE International Symposium on Hardeare-Oriented Security and Trust, 2011, pp. 142–147.
[18] Ja Chun Ku and Yehea Ismail, “A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay,” in Proc. IEEE International Symposium on Circuits and Systems, 2007, pp. 3736–3739.
[19] Yannis Tsividis and Colin MacAndrew, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1999.
[20] J. Tzou, J, C. Yao, C, R. Cheung, and H. Chan, “The temperature dependence of threshold voltages in semiconductor cmos,” IEEE Journal of Electron Device Letters, vol. 6, no. 5, pp. 250–252, May 1985.
[21] Neil H. E. Weste and David Money Harris, CMOS VLSI DESIGN: A CIRCUITS AND SYSTEMS PERSPECTIVE. Boston: Addison-Wesley, 2010.
[22] Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, and Lukas P.P.P. van Ginneken, “Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs,” in Proc. Design Automation Conference, 2001, pp. 567–572.
[23] Thermal Runaway. [Online]. Available: https://en.wikipedia.org/wiki/Thermal_runaway.
[24] Massoud Pedram and Shahin Nazarian, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods,” Proceeding of the IEEE, vol. 94, no. 8, pp. 1487–1501, August 2006.
[25] Yan Zhang, Dharmesh Parikh, Karthik Sankaranarayanan, Kevin Skadron, and Mircea Stan, “Hotleakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects,” Dept. of Electrical, Computer Engineering, and Computer Science University of Virginia, Virginia, Technical Report, March 2003.
[26] Electromigration. [Online]. Available: https://en.wikipedia.org/wiki/Electromigration.
[27] James R. Black, “Electromigration - A Brief Survey and Some Recent Results,” IEEE Transaction Electron Devices, vol. E-16, no.4, pp. 338–347, April 1969.
[28] IDC. (2009). Beyond organisational boundaries: answering the enterprise computing challenge. [Online]. Available: http://uk.idc.com.
[29] Leila Choobineh and Ankur Jain, “Analytical Solution for Steady-State and Transient Temperature Fields in Vertically Stacked 3-D Integrated Circuits,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 2, no. 12, pp. 2031–2039, Dec. 2012.
[30] Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, and David Tarjan, “Temperature-Aware Microarchitecture,” in Proc. International Symposium on Computer Architecture, 2003, pp. 2–13.
[31] Wei Huang, Eric Humenay, Kevin Skadron, and Mircea R. Stan, “The Need for a Full-Chip and Package Thermal Model for Thermally Optimized IC Designs,” in Proc. International Symposium on Low Power Electronics and Design, 2005, pp. 245–250.
[32] Wei Huang, Shougata Ghosh, Siva Velusamy, Karthik Sankaranarayanan, Kevin Skadron, and Mircea R. Stan, “HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design,” IEEE Transactions on Very Large Scale Integration Systems, vol. 14, no. 5, pp. 501–513, May 2006.
[33] Wei Huang, Karthik Sankaranarayanan, Kevin Skadron, Robert J. Ribando, and Mircea R. Stan, “Accurate Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model,” IEEE Transactions on Computers, vol. 57, no. 9, pp. 1277–1288, Sept. 2008.
[34] Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, and David Atienza, “3D-ICE: Fast Compact Transient Thermal Modeling for 3D ICs with Inter-tier Liquid Cooling,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, 2010, pp. 463–470.
[35] “3D-ICE 2.2.6 User Guide,” École polytechnique fédérale de Lausanne, Lausanne, 2016.
[36] Arvind Sridhar, Alessandro Vincenzi, David Atienza, and Thomas Brunschwiler, “3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs,” IEEE Transactions on Computers, vol. 63, no. 10, pp. 2576–2589, Oct. 2014.
[37] Yonghong Yang, Zhenyu Gu, Changyun Zhu, Robert P. Dick, and Li Shang, “ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 86–99, Jan. 2007.
[38] Ting-Yuan Wang and Charlie Chung-Ping Chen, “3-D Thermal-ADI: A Linear-Time Chip Level Transient Thermal Simulator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 12, pp. 1434–1445, Dec. 2002.
[39] Hai Wang, Duo Li, Sheldon X.-D. Tan, Murli Tirumala, and Ashish X. Gupta, “Composable Thermal Modeling and Characterization for Fast Temperature Estimation,” in Proc. IEEE Conference on Electrical Performance of Electronic Packaging and Systems, 2010, pp. 185–188.
[40] ANSYS. [Online]. Available: http://www.ansys.com.
[41] “ANSYS Icepak Tutorials,” ANSYS, PA, 2013.
[42] Kiyomi Yoshinari and Takuro Kanazawa, “Feasibility Study for Thermal Conductivity Simulation by Coupling between Admittance Matrix Method and Finite Elemental Method,” in Proc. 15th European Power Electronics and Applications, 2013, pp. 1–8.
[43] Amir Zjajo, Nick van der Meijs, and Rene van Leuken, “Thermal Analysis of 3D Integrated Circuits Based on Discontinuous Galerkin Finite Element Method,” in Proc. IEEE International Symposium on Quality Electronic Design, 2012, pp. 117–222.
[44] Jianyong Xie and Madhavan Swaminathan, “Electrical-Thermal Co-Simulation of 3D Integrated Systems with Micro-Fluidic Cooling and Joule Heating Effects,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 234–246, Jan. 2011.
[45] Wenjian Yu, Tao Zhang, Xiaolong Tuan, and Haifeng Qian, “Fast 3-D Thermal Simulation for Integrated Circuits With Domain Decomposition,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 12, pp. 2014–2018, Dec. 2013.
[46] Zyad Hassan, Nicholas Allec, Li Shang, Robert P. Dick, Vishak Venkatraman, and Ronggui Yang, “Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 6, pp. 860–873, June 2009.
[47] Ibrahim Guven, Cho Lik Chan, and Erdogan Madenci, “Transient Two-Dimensional Thermal Analysis of Electronic Packages by the Boundary Element Method,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 476–486, Aug. 1999.
[48] Travis Kemper, Yan Zhang, Zhixi Bian, and Ali Shakouri, “ULTRAFAST TEMPERATURE PROFILE CALCULATION IN IC CHIPS,” in Proc. 12th International Workshop on Thermal Investications of ICs, 2006, pp. 133–137.
[49] Amirkoushyar, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, and Ali Shakouri, “Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices,” IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 11, pp. 2366–2379, Nov. 2014.
[50] Amirhoushyar Ziabari and Ali Shakouri, “Fast Thermal Simulations of Vertically Integrated Circuits (3D ICs) Including Thermal Vias,” in Proc. IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2012, pp. 588–596.
[51] Samson Melamed, Thorlindur Thorolfsson, Robert Harris, Shivam Priyadarshi, Paul Franzon, Michael B. Steer, and W. Rhett Davis, “Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 5, pp. 676–689, May 2012.
[52] S. Delić and Ž. Jurić, “Some Improvements of the Gaussian Elimination Method for Solving Simultaneous Linear Equations,” in Proc. 36th International Convention on Information and Communication Technology, Electronics and Microelectronics, 2013, pp. 96–101.
[53] Zan Li, Fuhui Zhou, Jiangbo Si, Peihan Qi, and Lei Guan, “Feasibly efficient cooperative spectrum sensing scheme based on Cholesky decomposition of the correlation matrix,” IET Communications, vol. 10, no. 9, pp. 1003–1011, 2016.
[54] Juliet N. Gaithuru, Mazleena Salleh, and Ismail Mohamad, “NTRU Inverse Polynomial Algorithm Based on the LU Decomposition Method of Matrix Inversion,” in Proc. IEEE Conference on Application, Information and Network Security, 2017, pp. 1–6.
[55] Liu Hongxia and Feng Tianziang, “Study on the Convergence of Sloving Linear Equations by Gauss-Seidel and Jacobi Method,” in Proc. 11th International Conference on Computational Intelligence and Security, 2015, pp. 100–103.
[56] Zhihui Zhang, Qinghai Miao, and Ying Wang, “CUDA-Based Jacobi’s Iterative Method,” in Proc. International Forum on Computer Science-Technology and Applications, 2009, pp. 259–262.
[57] Noreen Jamil, Johannes Muller, Christof Lutteroth, and Gerald Weber, “Speeding up SOR Solvers for Constraint-Based GUIs with a Warm-Start Strategy,” in Proc. International Conference on Digital Information Management, 2013, pp. 268–273.
[58] Xiuke Yan, Xiaoyu Han, Dongyang Wu, Dexin Xie, Baodong Bai, and Ziyan Ren, “Research on Preconditioned Conjugate Gradient Method Based on EBE-FEM and the Application in Electromagnetic Field Analysis,” IEEE Transactions on Magnetics, vol. 53, no. 6, pp. 7202704, June. 2017.
[59] Jianping Zhu, Yingying Liu, Wei Zhuang, and Wanchun Tang, “Fast thermal analysis of TSV-based 3D-ICs by GMRES with symmetric successive over-relaxation (SSOR) preconditioning,” in Proc. IEEE Electrical Design of Advanced Packaging and Systems Symposium, 2015, pp. 178–181.
[60] Yousef Saad, “SPARSKIT: a basic tool kit for sparse matrix computations,” Department of Computer Science and Engineering, University of Minnesota, Version 2, 1994.
[61] Nathan Bell and Michael Garland, “Implementing Sparse Matrix-Vector Multiplication on Throughput-Oriented Processors,” in Proc. The Conference on High Performance Computing Networking, Storage and Analysis, 2009, pp. 1–11.
[62] Xue-Xin Liu, Kuangya Zhai, Zao Liu, Kai He, Sheldon X.-D. Tan, and Wenjian Yu, “Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms,” IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 3, pp. 575–579, March 2015.
[63] Zhuo Feng and Peng Li, “Fast Thermal Analysis on GPU for 3D-ICs with Integrated Microchannel Cooling,” in Proc. IEEE International Conference on Computer-Aided Design, 2010, pp. 551–555.
[64] Yi-Li Lin and Alvin W. Y. Su, “Function Verifications for SoC Software/Hardware Co-Design: From Virtual Platform to Physical Platform,” in Proc. 2011 IEEE International SoC Conference, 2011, pp. 201–206.
[65] Zhe-Mao Hsu, I-Yao Chuang, Wen-Chien Su, Jen-Chieh Yeh, Jen-Kuei Yang, and Shau-Yin Tseng, “System Performance Analyzes on PAC Duo ESL Virtual Platform,” in Proc. Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2009, pp. 406–409.
[66] I-Yao Chuang, Chi-Wen Chang, Tso-Yi Fan, Jen-Chieh Yeh, Kung-Ming Ji, Jui-Liang Ma, An-Yeu Wu, and Shih-Yin Lin, “PAC Duo SoC Performance Analysis with ESL Design Methodology,” in Proc. IEEE 8th International Conference on ASIC, 2009, pp. 399–402.
[67] Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, and Yi-Siou Chen, “System Power Analysis with DVFS on ESL Virtual Platform,” in Proc. IEEE International SoC Conference, 2011 pp. 93–98.
[68] Wen-Tsan Hsieh, Jen-Chieh Yeh, and Shi-Yu Huang, “PAC Duo System Power Estimation at ESL,” in Proc. 15th Asia and South Pacific Design Automation Conference, 2010, pp. 815–820.
[69] Sumeet S. Kumar, Amir Zjajo, and Rene van Leuken, “Ctherm: An Integrated Framework for Thermal-Functional Co-Simulation of Systems-on-Chip,” in Proc. 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2015, pp. 674–681.
[70] Tayeb Bouhadiba, Matthieu Moy, Florence Maraninchi, Jerome Cornet, Laurent Maillet-Contoz, and Ilija Materic, “Co-Simulation of Functional SystemC TLM Models with Power/Thermal Solvers,” in Proc. IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2013, pp. 2176–2181.
[71] Yunus A. Cengel, HEAT TRANSFER: A Practical Approach. New York: McGraw-Hill, 2002.
[72] Theodore L. Bergman, Adrienne S. Lavine, Frank P. Incropera, and David P. Dewitt, FUNDAMENTALS OF HEAT and MASS TRANSFER. New York: John Wiley, 2011.
[73] Unberto Berardi and Matteo Naldi, “The impact of the temperature dependent thermal conductivity of insulating materials on the effective building envelope performance,” ELSEVIER Energy and Buildings, pp. 262–275, March 2017.
[74] CUDA. [Online]. Available: https://en.wikipedia.org/wiki/CUDA
[75] John Cheng, Max Grossman, and Ty Mckercher, Professional CUDA C Programming. New York: John Wiley & Sons, 2014.
[76] Shu-Hsuan Chou, Che-Neng Wen, Yan-Ling Liu, and Tien-Fu Chen, “VeriC: A Semi-Hardware Description Language to Bridge the Gap Between ESL Design and RTL Models,” in Proc. 10th International Symposium on Quality Electronic Design, 2009, pp. 535–540.
[77] Dai Araki, Atsushi Nakamura, and Masayuki Miyama, “Model-based SoC design using ESL environment,” in Proc. International SoC Desin Conference, 2010, pp. 83–86.
[78] Maman Abdurohman, Kuspriyanto, Sarwono Sutikno, and Arif Sasongko, “Transaction Level Modeling for Early Verification on Embedded System Design,” in Proc. IEEE International Conference on Computer and Information Science, 2009, pp. 277–282.
[79] Frank Rogin and Rolf Drechsler, Debugging at the Electronic System Level. Berlin: Springer, 2010.
[80] IC Design Flow. [Online]. Available: https://en.wikipedia.org/wiki/Physical_design_(electronics)
[81] Karsten Einwich, Requirements specification for SystemC Analog Mixed Signal (AMS) extensions. March 8, 2010.
[82] L. Cai and D. Gajski, “Transaction level modeling: an overview,” in Proc. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003, pp. 19–24.
[83] Xiaoye S. Li, James W. Demmel, John R. Gilbert, Laura Grigori, Meiyue Shao, and Ichitaro Yamazaki, “SuperLU Users’s Guide,” University of Califoornia, Berkeley, CA, 2011.
[84] Mark Slee, Aditya Agarwal, and Marc Kwiatkowski, “Thrift: Scalable Cross-Language Services Implementation,” Technology Report, Facebook, Palo Alto, CA, USA, April 2007.
[85] Pierre Michaud and Yiannakis Sazeides, “ATMI: Analytical Model of Temperature in Microprocessors,” in Proc. Third Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), 2007.
[86] CUDA C PROGRAMMING GUIDE. [Online]. Available: http://docs.nvidia.com/cuda//pdf/CUDA_C_Programming_Guide.pdf
[87] CUDA Parallel Programming Model. [Online]. Available: http://www.cse.unsw.edu.au/~pls/cuda-workshop09/slides/02_CUDAParallelProgrammingModel.pdf.
[88] Kevin Skadron, Tarek Abdelzaher, and Micrea R. Stan, “Control-Theoretic Techniques and Thermal RC Modeling for Accurate and Localized Dynamic Thermal Management,” in Proc. International Symposium on High-Performance Computer Architecture, 2002, pp. 17–28.
[89] Zhiping Yu, Dan Yergeau, and Robert W. Dutton, “Full Chip Thermal Simulation,” in Proc. IEEE International Symposium on Quality Electronic Design, 2000, pp. 145–149.
[90] Bert K. Larkin, “Some Stable Explicit Difference Approximations to the Diffusion Equation,” Mathematics of Computation, vol. 18, no. 86, pp. 196–202, 1964.
[91] Ruixia Cui and Mingjun Wei, “Research and Application of Successive Over-Relaxation Iterative Algorithm,” in Proc. Proceedings of International Conference on Electronic & Mechanical Engineering and Information Technology, 2011, pp. 3856–3858.
[92] Yogendra Joshi and Pramod Kumar, Energy Efficient Thermal Management of Data Centers. New York: Springer, 2012.
[93] Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, and Huang-Lun Lin, “Stacking Memory Architecture Exploration for Three-Dimensional Integrated Circuit in 3-D PAC,” in Proc. IEEE international SoC Conference, 2012, pp. 317–321.
[94] Lih-Yih Chiou, Liang-Ying Lu, Zhao-Hong Chen, Yu-Hsiung Su, Jen-Chieh Yeh, Yi-Fan Chen, and Shih-Che Lin, “System Thermal Analysis of 3D IC on ESL Virtual Platform,” in Proc. IEEE International SoC Design Conference, 2013, pp.394–397.
[95] T. B. Y. Chen, A. C. Y. Yuen, G. H. Yeoh, V. Timchenko, S. C. P. Cheung, Q. N. Chan, W. Yang, and H. Lu, “Numerical study of fire spread using the level-set method with large eddy simulation incorporating detailed chemical kinetics gas-phase combustion model,” Journal of Computational Science, vol. 24, pp. 8–23, January 2018.
[96] Liang-Ying, Lu, Ching-Yao, Chang, “A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling,” in Proc. IEEE Asia and South Pacific Design Automation Conference, 2016, pp. 17–18.
[97] Matthew R. Guthaus, Jeffrey S. Ringenberg, and Dan Ernst, “MiBench: A free, commercially representative embedded benchmark suit,” in Proc. IEEE International Workshop on Workload Characterization, 2001, pp. 3–14.
[98] Steven Cameron Woo, Moriyoshi Ohara, and Evan Torrie, “The SPLASH-2 Programs: Characterization and Methodological Considerations,” in Proc. 22nd Annual International Symposium on Computer Architecture, 1995, pp. 24–26.