電源網路規劃在實體電路設計中成為越來越重要的議題，隨著製程的進步，在晶片裡的電路元件數量快速增加及連線複雜度大幅提升，會導致功率消耗更加嚴重及繞線困難增加。由於設計不良的電源網路會為了滿足IR-drop限制與解決EM效應問題而浪費較多的繞線資源，另一方面隨著現代設計的複雜化，晶片設計中的預先擺置模塊數量大為增加，傳統用單一長度的垂直線段進行線段擺置的方式將使得設計彈性降低從而導致區域較為嚴重的繞線擁擠。因此，本論文提出一個電源網路規劃的流程，其主要分為二個部分，第一部分考量預先擺置模塊切割繞線區域並應用線性規劃方法來計算電源線段所需的適當面積以滿足每個子區域的IR-drop限制條件。在第二部分，我們提出動態規劃演算法調整電源線段的位置。實驗結果證明本論文的方法不僅可以符合電壓衰退條件，更可以藉由節省電源線段面積以及考慮預先擺置模塊進行電源線段擺置以提升繞線階段的可繞度。

Powerplanning is a critical step in the physical design, and the result has a fatal impact on the quality of a design. A classical P/G network focuses on reducing routing areas to satisfy voltage drop and electromigration constraints, and a regular power mesh is adopted in a chip. As a modern design contains more and more macros, powerplanning becomes more complex, and a regular power mesh would waste more routing resource and may make routing congestion more severe in local regions. In order to save routing resource and increase routability, this paper proposes a delicate method to perform powerplanning. First, according to the locations of macros, we construct a row-based power mesh to facilitate connection of these macros and increase routability. Besides, we also find an effective power stripe width which can reduce wastage of routing resource and reduce voltage drop of a design. Third, a more precise cost is used to determine locations of power stripes in a region based on the dynamic programming algorithm. The experimental results show that our methodology can significantly improve routability in a design with several macros.

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