本論文呈現一個內建晶片上參考電源緩衝器且使用本論文所提出之「低複雜度碼相依參考電源漣波抑制(LCRRS)技術」之十一位元每秒取樣二千萬次的單通道逐漸趨近式類比數位轉換器。
本論文所提出之技術，能夠抑制使用常見電容切換方法的逐漸趨近式類比數位轉換器中所有的碼相依參考電源擾動。此外，與其他類似技術相較，其所需之補償電路複雜度，隨著切換步驟號碼只會線性上升，而非指數上升，因此能夠只使用少量的額外硬體，就能抑制差動非線性中的喇叭狀特徵，而且進一步節省參考電源產生器之功耗。
本設計以台積電180奈米CMOS標準1P6M製程實作晶片，其核心電路面積佔了0.563 mm2。使用本技術在1.8伏特電源供應、每秒二千萬次的取樣頻率及奈奎氏輸入頻率下，有效位元為10.33位元且總消耗功率為3.132毫瓦，每次的資料轉換所消耗的能量為121.7 fJ。使用本技術的差動及積分非線性，分別為 0.74/-0.70 LSB 和 0.67/-0.73 LSB，有別於未使用本技術的4.06/-1.00 LSB 和 INL of 4.19/-3.80 LSB。量測結果更近一步顯示，本技術能夠降低靜態效能對參考電源緩衝器功耗之敏感度。

A single-channel 11-bit 20-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference buffer and the proposed low-complexity code-dependent reference ripple suppression (LCRRS) technique is presented in this thesis.
The proposed technique is able to suppress all code-dependent reference perturbations in a SAR ADC using commonly-used switching procedures. Compared with similar techniques, the complexity of the proposed compensation hardware increases linearly instead of increasing exponentially with respect to the number of switching step, which suppresses the effect of trumpet-shaped feature in differential nonlinearity (DNL) and enables further power savings on the reference generator with little extra hardware.
The proof-of-concept prototype was fabricated in TSMC 180-nm CMOS technology. The core area occupies 0.563 mm2. At 1.8 V, sampling rate of 20 MS/s and Nyquist input, the effective number of bits (ENOB) is 10.33 bits and the total power consumption is 3.132 mW with the proposed technique, which results in a figure-of-merit (FoM) of 121.7 fJ/conversion-step. DNL and integral nonlinearity (INL) with the proposed technique are 0.74/-0.70 LSB and 0.67/-0.73 LSB, respectively, compared to DNL of 4.06/-1.00 LSB and INL of 4.19/-3.80 LSB without the proposed technique. The measurement results also show that the proposed technique renders the static performance less sensitive to the power consumption of the reference buffer.

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