不論是在生醫擷取系統、通訊系統或是影像處理系統等應用上，都必須要透過類比數位轉換器來實現類比訊號與數位訊號的介面轉換。在目前所存在的類比數位轉換器架構中，連續漸近式類比數位轉換器是非常適合在生醫訊號擷取系統的應用上，主要是因為連續漸近式類比數位轉換器有著高效能和中等轉換速度的優點。然而對於高解析度的連續漸近式轉換器而言，主要受到製成漂移而產生的電容不匹配問題以及比較器直流漂移的誤差，進而影響到高解析度的轉換器效能。一般來說，電容的不匹配問題和直流漂移的誤差會造成諧波失真並直接反映在輸出的功率頻譜上。因此必須要透過校正的技術來提升電路的效能以及確保整體系統的訊號品質。
本文提出一個前端式的數位校正技術，主要透過遞迴式離散傅立葉轉換器、遞迴式離散餘弦轉換器以及矩陣分析的方式來補償連續漸近式類比數位轉換器中電容不匹配和直流偏移的誤差。此校正技術主要是透過轉換器或是矩陣分析的方式，評估受到不匹配影響的真實數位類比轉換器電容陣列的電容比例，並在數位輸出端進行誤差的補償。此外遞迴式離散傅立葉轉換器和遞迴式離散餘弦轉換器的校正技術還可以抑制比較器中直流偏移的誤差問題。在遞迴式離散傅立葉轉換器以及遞迴式離散餘弦轉換器的設計上，因為只需要計算主頻和第三根諧波失真，所以分別只需要2N+2以及2N個乘法器，另外都需要4N+2個加法器。此外在轉換長度的設計上為4096點而在係數寬度設計上為24位元。
對於類比數位轉換器的測試應用而言，我們提出了一個具有前端式數位校正技術的自動測試平台。在此平台的設計上，我們使用數位控制碼來控制Arduino開發版中的高解析度數位類比轉換器，並利用Arduino開發板產生出測試系統中需要的弦波測試訊號以及時脈訊號。此外在此測試平台中，採用了離散傅立葉轉換器來量測類比數位轉換器的動態效能，同時也使用了遞迴式離散傅立葉轉換器來實現數位校正的技術。因此透過此自動測試平台，可以幫助設計者量測類比數位轉換器的動態效能，並可透過校正技術來改善轉換器的效能。
根據模擬以及量測的結果，本文所提出的校正技術能夠減少諧波失真的問題以及提升類比數位轉換器的整體效能。另外本文所提出的校正技術，不需要額外的類比電路以及擁有較低複雜度的數位演算法。相比較於傳統的傅立葉離散轉換器，遞迴式的離散傅立葉轉換器和離散餘弦轉換器有著可調整式長度、低複雜度、快速計算和低硬體成本等優點。此外與先進技術相比較，我們提出的矩陣式技術有這較低的運算複雜度，我們可以降低99%的乘法器運算以及99% 的加法器運算。因此透過本文所提出的校正技術能夠有效的幫助設計者補償轉換器的誤差並且提升整體效能。

Analog-to-digital converters (ADCs) are required for interfacing analog signals to digital signals in many applications, such as in biomedical acquisition systems, communication systems, or image processing systems. Among the existing ADC architectures, successive approximation (SAR) ADCs are popoular for their excellent energy efficiency and medium speed conversion, which makes them appropriate for use in biomedical signal acquisition. However, the high-performance limiataions that occur with SAR ADCs are mainly due to capacitor mismatch and DC offset, because of the problem of process variation. The capacitor mismatch and DC offset error in the characteristic function tends to immediately causes harmonic distortion, and these errors will then deteriorate the performance of the ADC. Calibration is thus essential to ensure system quality and enhance the performance of the ADC.
The foreground digital calibration method proposed in this work is based on the recursive discrete Fourier transform (RDFT), recursive discrete cosine transform (RDCT) and matrix-form analysis (MFA), and is used to compensate for the capacitor mismatch error for the SAR ADC. The RDFT, RDCT and MFA calibration method, can be applied to evaluate the real radix of a DAC capacitor array with a new digital output to compensate for the errors caused by capacitor mismatch. In addition, the RDFT and RDCT calibration techniques can also eliminate the DC offset of a comparator circuit. In this proposed method, the RDFT and RDCT calibration method only needs to calculate the main and third harmonic tones, so the computational complexity of the RDFT/RDCT algorithm requires a total of (2N+2)/2N multiplications and (4N+2) additions. In addition, the transform length is selected to 4,096 and the world length of coefficient is set to 24 bits.
For the ADC testing application, a self-testing platform with a foreground calibration technique for SAR ADC is presented. In this work, a high-accuracy DAC with digital control is used to generate the sinusoidal test signal. This signal is then implemented using an Arduino, and the clock signal is generated to test the ADCs. In addition, a fast Fourier transform (FFT) and RDFT processor is adopted to measure the dynamic performance and carry out the calibration, respectively. Therefore, this platform can help the designer to measure the dynamic performance of the ADC, and can also improve the performance of the ADC by using the proposed calibration technique.
According to the simulation and measurement results, the proposed calibration method can reduce the harmonic distortion and improve the performance of the ADC. Here, the proposed calibration method has the advantage that it does not require extra analog circuit or complex digital circuits. Therefore, the proposed calibration method that utilizes the RDFT and RDCT processor instead of the FFT processor has the advantage of variable transform length, lower complexity, faster computation and less hardware cost. Comparing the computational complexity of the MFA technique with other state-of-the-art approaches, the proposed MFA algorithm dramatically reduces the multiplication by 99% and addition by 99%. As aresult, the proposed method can help designers to compensate for errors and enhance the performance of the ADC.

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