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研究生： 鄧光宇
Teng, Kuang-Yu
論文名稱： 應用於鐵電場效電晶體記憶體內運算系統之元件變異感知穩健關鍵字辨識訓練
Device-Variation-Aware Training for Robust Keyword Spotting in FeFET-Based Compute-in-Memory Systems
指導教授： 盧達生
Lu, Darsen
張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2026
畢業學年度： 114
語文別： 英文
論文頁數： 147
中文關鍵詞： 關鍵字辨識 、記憶體內運算 、鐵電場效電晶體 、元件變異 、變異感知訓練
外文關鍵詞： keyword spotting, compute-in-memory, FeFET, device-to-device variation, variation-aware training
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    • 隨著邊緣人工智慧的快速發展，超低功耗且可長時間持續運作的關鍵字辨識系統需求日益增加。以鐵電場效電晶體（Ferroelectric Field-Effect Transistor, FeFET）為基礎之記憶體內運算（Compute-in-Memory, CIM）技術，由於具備非揮發性權重儲存與記憶體內運算能力，可有效降低待機功耗與資料搬移能耗，因此成為實現超低功耗邊緣人工智慧的重要技術。然而，FeFET 元件間變異所造成的類比運算誤差，將導致推論準確率下降，成為 FeFET-CIM 實際應用所面臨的重要挑戰。
    本論文提出一套適用於 FeFET-CIM 關鍵字辨識系統之硬體感知變異感知訓練（Hardware-Aware Variation-Aware Training）架構。所建立之可微分 FeFET-CIM 模型整合位元序列乘加運算、類比數位轉換器量化以及元件間變異等硬體特性，並導入兩階段訓練流程，包括傳統量化感知訓練（Quantization-Aware Training, QAT）與變異感知微調（Variation-Aware Fine-Tuning），使模型於訓練階段即可學習補償硬體所造成的運算誤差。
    本研究分別於 Software Accuracy、Hardware Accuracy 及 Hardware Accuracy with D2D Variation 三種執行條件下評估所提出方法的效能，並透過蒙地卡羅模擬分析不同硬體實例下的穩健性。實驗結果顯示，所提出之方法在理想執行條件下可維持與基準模型相近的推論準確率；在存在元件間變異時，則能顯著提升模型的推論準確率，同時有效降低不同硬體實例所造成的效能波動，展現良好的硬體穩健性。
    綜合而言，本研究證實硬體感知變異感知訓練能有效提升 FeFET-CIM 關鍵字辨識系統對元件間變異的容忍能力，為未來超低功耗邊緣人工智慧應用中部署高可靠度 FeFET-CIM 系統提供一種具可行性的解決方案。

    The rapid growth of edge artificial intelligence has created a strong demand for ultra-low-power, always-on keyword spotting (KWS) systems. Ferroelectric field-effect transistor (FeFET)-based compute-in-memory (CIM) is a promising solution because it reduces standby power and data-movement energy. However, device-to-device (D2D) variation introduces analog computation errors that degrade inference accuracy.
    This thesis proposes a hardware-aware variation-aware training framework for FeFET-CIM-based KWS systems. A differentiable FeFET-CIM model that captures bit-serial MAC computation, ADC quantization, and D2D variation is incorporated into a two-stage training procedure consisting of conventional quantization-aware training and variation-aware fine-tuning.
    The proposed framework is evaluated using Software Accuracy, Hardware Accuracy, and Hardware Accuracy with D2D Variation, where hardware robustness is assessed through Monte Carlo simulations. Experimental results show that the proposed method preserves comparable inference accuracy under ideal conditions while significantly improving robustness against D2D variation and reducing performance variability across different hardware realizations.
    These results demonstrate that hardware-aware variation-aware training is an effective approach for deploying robust FeFET-CIM-based keyword spotting systems for future ultra-low-power edge AI applications.

    摘要 I Abstract III TABLE OF CONTENTS V LIST OF TABLES IX LIST OF FIGURES X Chapter1 Introduction 1 1.1 Edge AI and the Memory Wall 1 1.2 Always-On Keyword Spotting and Normally-Off Operation 3 1.3 Non-Volatile Memory Technologies for Normally-Off Operation 4 1.4 Motivation: Robustness Without Extra Hardware Cost 6 1.5 Related Work and Research Positioning 7 1.6 Research Objectives and Contributions 9 1.7 Thesis Organization 10 Chapter2 Background: Neural Networks and DNN Accelerators 11 2.1 Neural Network Layers 11 2.1.1 Fully Connected Layers 12 2.1.2 Convolutional Layers 13 2.1.3 Pooling Layers 14 2.1.4 Activation Layers 15 2.1.5 Normalization Layers 16 2.2 Neural Network Training 17 2.2.1 Loss Function and the Training Objective 17 2.2.2 Backpropagation and Gradient Descent 18 2.2.3 Optimizers and Learning Rate 19 2.2.4 Generalization, Overfitting, and Regularization 20 2.2.5 Straight-Through Estimator (STE) 23 2.3 Audio Preprocessing and Spectrogram Representation 23 2.4 Quantization for Neural Network Inference 25 2.4.1 Numerical Formats and Precisions 25 2.4.2 Quantization Mapping Methods 27 2.4.3 Quantization Strategies: PTQ and QAT 29 2.5 Dataflow and Memory Mapping in DNN Accelerators 30 2.5.1 Memory Hierarchy in DNN Accelerators 31 2.5.2 Data Reuse and Dataflow Strategies 32 2.5.3 Memory Mapping and Stationary Dataflows 35 Chapter3 CIM Architectures, FeFET Devices, and Variation Mitigation 37 3.1 Principles of Compute-in-Memory 37 3.2 SRAM-based CIM Architectures 40 3.2.1 6T SRAM Bit-Cell 41 3.2.2 Current-Domain MAC Readout 44 3.2.3 Charge-Domain MAC Readout 46 3.2.4 Limitations of SRAM-based CIM 47 3.3 NVM-based CIM and FeFET Devices 48 3.3.1 Ferroelectric Materials and Properties 49 3.3.2 FeFET Operating Principle 50 3.3.3 Non-Ideal Effects of FeFET Devices 51 3.3.4 FeFET-Based CIM for Normally-Off Operation 53 3.4 Mitigation of D2D Variation 54 3.4.1 Device-Level Approaches 54 3.4.2 Circuit-Level Approaches 55 3.4.3 Architecture-Level Approaches 58 3.4.4 Cost Comparison of Hardware-Level Mitigation 59 3.5 Algorithm-Level Mitigation of D2D Variation 61 3.6 Chapter Summary 63 Chapter4 Proposed FeFET-CIM Modeling and Variation-Aware Training Framework 64 4.1 Overview of the Proposed Framework 64 4.2 Quantized KWS Model 65 4.2.1 Network Architecture 66 4.2.2 Quantization Scheme 67 4.2.3 Integer Inference Flow 67 4.2.4 im2col-based Input Transformation 68 4.3 Proposed FeFET-CIM Architecture 69 4.3.1 Macro Organization and Array Partitioning 69 4.3.2 Bit-plane Weight Mapping 71 4.3.3 Bit-Serial MAC Operation 72 4.3.4 Column Current Accumulation and ADC 72 4.3.5 Integer Output Generation 73 4.4 FeFET D2D Variation Modeling 73 4.4.1 FeFET Cell Current Model 74 4.4.2 Series Resistance Model 75 4.4.3 Impact on MAC Computation 75 4.5 Variation-Aware Training 77 4.5.1 Differentiable CIM Forward 77 4.5.2 STE-based Variation Injection 78 4.5.3 Variation Bank Resampling 79 4.5.4 Two-Stage Training 79 4.6 Chapter Summary 80 Chapter5 Experimental Results and Discussion 81 5.1 Experimental Setup 81 5.1.1 Dataset and Input Features 81 5.1.2 Training Configuration 82 5.2 Evaluation Metrics and Execution Conditions 82 5.3 Effectiveness of Variation-Aware Training 84 5.4 Sensitivity Analysis of FeFET Device Parameters 87 5.4.1 Effect of D2D Variation 87 5.4.2 Effect of ON/OFF Ratio 89 5.4.3 Effect of Series Resistance 92 5.4.4 Summary of Sensitivity Analysis 94 5.5 Effect of Transient Bit Errors and Stuck-At Faults 95 5.6 Class-Level Impact of D2D Variation 97 5.7 Chapter Summary 102 Chapter6 Conclusion and Future Work 103 6.1 Conclusion 103 6.2 Future Work 104 Answer to thesis defense questions 106 Bibliography 113 Appendix A Analytical Model of Series-Resistance Compensation 120 A.1 Current Compression Model 120 A.2 Compressed ON/OFF Currents and the Effective ON/OFF Ratio 121 A.3 Suppression of Device-to-Device Variation 121 A.4 Compensated ADC Reconstruction and its Residual Error 122 A.4.1 Derivation of the Reconstructed Code 123 A.4.2 Derivation of the Random Residual 125 A.5 Error Budget and Decision Rule 127 A.6 Boundaries of the Usable Operating Range 128 A.6.1. Lower Boundary — Random-Dominated Limit 128 A.6.2. Upper Boundary — Systematic-Dominated Limit 129 A.6.3. Behavior Beyond the Upper Boundary 130 A.6.4. Usable Range 130 A.7 Assumptions and Limitations 131 A.8 Summary of Derived Expressions 132

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